David Anderson
2ebf399d62
vram/MemArbiter: remove MemArbiterClient, not needed right now
2024-09-08 22:44:39 -07:00
David Anderson
eca95e0fb6
vram/VRAMCore: correct exports of the vram types
2024-09-08 15:37:47 -07:00
David Anderson
913c407224
hardware/sentinel65x: comment out logic
...
I'm not quite ready to define top-levels yet, and having this incomplete
code here makes 'inv build .' fail.
2024-09-08 15:16:34 -07:00
David Anderson
e5aabcbf4a
vram/MemArbiter: remove unnecessary wires and fields
...
While iterating many redundant bits were added. This removes them again,
keeping just (I think) the minimum necessary for the arbitrators to work.
2024-09-08 15:13:47 -07:00
David Anderson
519eddc552
vram/MemArbiter: fix bug with write conflict avoidance
...
Now that all arbiter ports can request to write, arbitration must check
both (write, read) and (read, write) conflicts, not just (write, read).
2024-09-08 15:02:55 -07:00
David Anderson
191cd1bfa2
vram: document MemArbiter, fix round-robin ordering bug
2024-09-08 14:10:52 -07:00
David Anderson
f31f64f5a2
vram: refactor MemArbiter into separate arbiters
...
Rather than hardcode one architecture for GARY, the arbiters
are now split and can be allocated per-port. The arbiter interface
includes plumbing so that one arbiter can propagate a write conflict
to another, so it can still implement multi-port arbitration as long
as every client is statically allocated to one port.
2024-09-08 13:26:25 -07:00
David Anderson
2760bad965
vram: move VRAM to VRAMCore, in prep for arbitrated VRAM
2024-09-08 09:28:28 -07:00
David Anderson
69b7ce7f9e
vram: adjust the MemoryArbiterClient interface a little
2024-09-08 09:27:25 -07:00
David Anderson
81e5264d22
vram: make arbiter clients and servers connectable
2024-09-07 19:49:43 -07:00
David Anderson
aa048537ef
vram/MemArbiter: rewrite to use client/server idioms
...
In preparation for making the two Connectable and defining an
arbitrated memory client/server for VRAM access.
2024-09-07 16:58:11 -07:00
David Anderson
b2b2c14009
vram/VRAM: finish the top-level VRAM module
...
Well, for now at least. It can build 112KiB and 128KiB memories that
seem to synthesize to something reasonable.
2024-09-07 16:04:21 -07:00
David Anderson
dd551ce09b
tasks.py: fix typo in synth process
2024-09-07 16:03:52 -07:00
David Anderson
fc4b212139
compile all tests before running them, so the outputs are grouped
2024-09-07 12:15:33 -07:00
David Anderson
6e84e9c689
adjust 'inv genclk' to allow per-hardware PLLs
2024-09-07 12:11:27 -07:00
David Anderson
77b772c7ee
tasks.py: improve handling of Bluespec libdirs
...
To help divvy up the sources better, the build now makes a libpath
consisting of all directories that have bsv files in them, with a few
exceptions: hardware subdirs are target-specific so only get used if
they're the current build target. Experiments are random crap so get
the same treatment. And the 'sim' dir is only test helpers, so they
only get pulled in by tests.
2024-09-07 10:31:32 -07:00
David Anderson
25d1806590
lib/ClockOut: hack module to export a clock as an ordinary signal
...
Used to output a clock signal from an FPGA pin. The resultant output
signal is unclocked, so can be presented to any output at will.
2024-09-07 10:06:50 -07:00
David Anderson
5e997201db
hardware/sentinel65x: move top-level hw module to hw subdir
2024-09-07 10:04:36 -07:00
David Anderson
6fd040565c
Grab the inout port fixer from bsc tree, wire it in
...
Yosys doesn't understand Verilog-2001 port aliases. Unfortunately
bsc uses those to represent inout ports because it's the only way
to represent a particular kind of shared bus in Verilog source code.
Thankfully, a kind soul at Bluespec Inc made a perl script that
transforms the port alias construct into regular verilog-1995, which
works fine in cases like mine where the only user of the inout port
is a TriState module which tears it apart into separate
input/output/enable signals for the rest of bsc to work with.
2024-09-06 21:26:39 -07:00
David Anderson
0005ad6fe5
sentinel65x/PLL: update PLL settings, fix generator
2024-09-06 21:18:00 -07:00
David Anderson
d960eee973
flake.lock: update tools
2024-09-06 21:17:32 -07:00
David Anderson
f61328dac4
experiments/primitive_ram: clean up old testing code
2024-09-06 16:23:49 -07:00
David Anderson
930f9f7078
sentinel65x: start of Sentinel 65X top-level glue, with a PLL module
...
The PLL generates a 100MHz clock for GARY, 10MHz for the CPU and
system bus, and 25MHz for VGA out.
2024-09-06 16:21:25 -07:00
David Anderson
f7cb4b6ba2
vram/VRAM: early VRAM implementation
...
Only checked up to mkByteRAMArray, main VRAM still WIP
2024-09-06 16:11:55 -07:00
David Anderson
7560199251
tasks: support running nextpnr with a generic ulx3s pin map
...
This is handy for quick experiments, rather than having to define a
bespoke pin map for each experiment.
2024-09-06 16:11:03 -07:00
David Anderson
2953106ec7
lib/ECP5_RAM: mark interfaces always_ready
...
Elides a couple of unnecessary signals from the design
2024-09-06 16:10:22 -07:00
David Anderson
ab20db44f4
vram: rename MemoryArbiter to something shorter
...
As I implement the whole transaction-level modeling thing with
arbitration, the interface names are getting longer and longer.
2024-09-06 10:04:20 -07:00
David Anderson
7f10694371
vram: get rid of old commented code
2024-09-06 00:13:42 -07:00
David Anderson
f010693b9b
vram: compact the test output even more
2024-09-06 00:08:14 -07:00
David Anderson
71f422b8c1
vram: fix up documentation for MemoryArbiterWriter
2024-09-06 00:02:23 -07:00
David Anderson
e0d156cdd1
vram: a little more formatting of the vram test
...
Make it a bit more compact, for large test runs
2024-09-06 00:00:25 -07:00
David Anderson
d41ca7daae
vram: tidy up formatting
2024-09-05 23:51:21 -07:00
David Anderson
60348fefd2
vram: one more arbiter test for port conflicts
2024-09-05 23:46:01 -07:00
David Anderson
5e22d03e15
vram: implement a MemoryArbiter for VRAM
2024-09-05 23:39:21 -07:00
David Anderson
2cd172cc73
tasks.py: add sim directory when running tests
...
So that bluesim can find the DP16KD simulation model.
2024-08-31 00:00:59 -07:00
David Anderson
efb5327f53
lib: clean up ECP5_RAM.v a bit
2024-08-31 00:00:41 -07:00
David Anderson
119eeceaef
Add some early testing harness for the sim DP16KD
2024-08-30 22:14:10 -07:00
David Anderson
a4a10becbf
tasks.py: print one more intermediate output path
2024-08-30 20:06:36 -07:00
David Anderson
a0892fefcd
sim/tb: add "bad" signals to make it easier to see wrong outputs
2024-08-30 20:00:11 -07:00
David Anderson
b913afd416
sim/tb: add wanted output signal, to help see incorrect outputs
2024-08-30 19:56:08 -07:00
David Anderson
0b384c6619
sim: implementation of a simulation model DP16KD
...
Not fully verified with tests yet, WIP
2024-08-30 18:54:54 -07:00
David Anderson
e57f7e05b0
lib/ECP5_RAM: fixups based on checking synth output
2024-08-23 00:22:48 -07:00
David Anderson
febd840be0
Add svlint config
2024-08-23 00:21:15 -07:00
David Anderson
6666c1ca2d
flake.nix: fix up xdot, add systemverilog linter
2024-08-23 00:20:45 -07:00
David Anderson
5d16ce23aa
tasks.py: adjust yosys script
2024-08-23 00:20:31 -07:00
David Anderson
b73a211ec4
lib/ECP5_RAM: clean up old core, fix error in module docstring
2024-08-20 19:25:04 -07:00
David Anderson
1ccd1b0072
lib/DelayLine: add a bit more documentation
2024-08-20 09:15:52 -07:00
David Anderson
2a8689564c
tasks.py: remove debug message
2024-08-20 09:13:36 -07:00
David Anderson
5df41d4b94
lib: use DelayLine in ECP5_RAM
...
Cleans up the code nicely, and still produces the correct logic.
2024-08-20 00:54:50 -07:00
David Anderson
f1e705fd31
lib: add more documentation
2024-08-20 00:29:32 -07:00