lib/ClockOut: hack module to export a clock as an ordinary signal
Used to output a clock signal from an FPGA pin. The resultant output signal is unclocked, so can be presented to any output at will.
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package ClockOut;
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interface ClockOut;
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method bit value();
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endinterface
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import "BVI" ClockOut =
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module mkClockOut(ClockOut);
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default_reset no_reset;
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default_clock clk (CLK, (* unused *)GATE);
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method CLK_BIT value() clocked_by(no_clock);
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schedule value CF value;
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endmodule
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endpackage
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module ClockOut(input CLK, output CLK_BIT);
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assign CLK_BIT = CLK;
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endmodule
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