lib/ClockOut: hack module to export a clock as an ordinary signal

Used to output a clock signal from an FPGA pin. The resultant output
signal is unclocked, so can be presented to any output at will.
This commit is contained in:
David Anderson 2024-09-06 21:08:51 -07:00
parent 5e997201db
commit 25d1806590
2 changed files with 19 additions and 0 deletions

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lib/ClockOut.bsv Normal file
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package ClockOut;
interface ClockOut;
method bit value();
endinterface
import "BVI" ClockOut =
module mkClockOut(ClockOut);
default_reset no_reset;
default_clock clk (CLK, (* unused *)GATE);
method CLK_BIT value() clocked_by(no_clock);
schedule value CF value;
endmodule
endpackage

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lib/ClockOut.v Normal file
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module ClockOut(input CLK, output CLK_BIT);
assign CLK_BIT = CLK;
endmodule