sentinel65x/PLL: update PLL settings, fix generator
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@ -1,6 +1,6 @@
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package PLL;
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// Frequencies: FPGA 100MHz, CPU 10MHz, VGA 25MHz
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// Frequencies: FPGA 100MHz, CPU 8MHz, VGA 25MHz
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//
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// To regenerate, see 'inv genclk -h'
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@ -6,13 +6,13 @@ module PLL
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(
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input CLK_REF, // 25 MHz, 0 deg
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output CLK_MAIN, // 100 MHz, 0 deg
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output CLK_CPU, // 10 MHz, 0 deg
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output CLK_CPU, // 8 MHz, 0 deg
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output CLK_VGA, // 25 MHz, 0 deg
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output locked
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);
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(* FREQUENCY_PIN_CLKI="25" *)
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(* FREQUENCY_PIN_CLKOP="100" *)
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(* FREQUENCY_PIN_CLKOS="10" *)
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(* FREQUENCY_PIN_CLKOS="8" *)
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(* FREQUENCY_PIN_CLKOS2="25" *)
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(* ICP_CURRENT="12" *) (* LPF_RESISTOR="8" *) (* MFG_ENABLE_FILTEROPAMP="1" *) (* MFG_GMCREF_SEL="2" *)
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EHXPLLL #(
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@ -30,7 +30,7 @@ EHXPLLL #(
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.CLKOP_CPHASE(2),
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.CLKOP_FPHASE(0),
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.CLKOS_ENABLE("ENABLED"),
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.CLKOS_DIV(60),
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.CLKOS_DIV(75),
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.CLKOS_CPHASE(2),
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.CLKOS_FPHASE(0),
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.CLKOS2_ENABLE("ENABLED"),
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2
tasks.py
2
tasks.py
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@ -205,7 +205,7 @@ def clean(c):
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@task
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def genclk(c, in_mhz=25, main_mhz=100, cpu_mhz=10, vga_mhz=25):
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out = Path("gary/PLL.v")
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out = Path("sentinel65x/PLL.v")
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c.run(f"ecppll -f {out} --module PLL --clkin_name CLK_REF --clkin {in_mhz} --clkout0_name CLK_MAIN --clkout0 {main_mhz} --clkout1_name CLK_CPU --clkout1 {cpu_mhz} --clkout2_name CLK_VGA --clkout2 {vga_mhz}")
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bsv_out = out.with_suffix(".bsv")
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with open(bsv_out) as f:
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