vram: rename MemoryArbiter to something shorter

As I implement the whole transaction-level modeling thing with
arbitration, the interface names are getting longer and longer.
This commit is contained in:
David Anderson 2024-08-31 13:25:04 -07:00
parent 7f10694371
commit ab20db44f4
3 changed files with 32 additions and 32 deletions

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@ -1,6 +1,6 @@
package Top;
import MemoryArbiter::*;
import MemArbiter::*;
import Vector::*;
import DReg::*;
import DelayLine::*;
@ -30,7 +30,7 @@ module mkTop(Top);
Vector#(2, Reg#(Maybe#(WriteReq))) wrin <- replicateM(mkDReg(tagged Invalid));
Vector#(4, Reg#(Maybe#(Addr))) rdin <- replicateM(mkDReg(tagged Invalid));
MemoryArbiter#(Addr) ret <- mkMemoryArbiter();
MemArbiter#(Addr) ret <- mkMemArbiter();
Reg#(Vector#(6, Bool)) ok <- mkReg(replicate(False));

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@ -1,52 +1,52 @@
package MemoryArbiter;
package MemArbiter;
import Vector::*;
export MemoryArbiterWriter(..);
export MemoryArbiterReader(..);
export MemoryArbiter(..);
export mkMemoryArbiter;
export MemArbiterWriter(..);
export MemArbiterReader(..);
export MemArbiter(..);
export mkMemArbiter;
// A MemoryArbiterWriter can request use of a memory port to read or
// A MemArbiterWriter can request use of a memory port to read or
// write to an address. When a request is feasible, grant() returns
// True in the same cycle.
(* always_ready *)
interface MemoryArbiterWriter#(type addr);
interface MemArbiterWriter#(type addr);
method Action request(Bool write, addr address);
method Bool grant();
endinterface
// MemoryArbiterReader can request use of a memory port to read from
// MemArbiterReader can request use of a memory port to read from
// an address. When a request is feasible, grant() returns True in the
// same cycle.
(* always_ready *)
interface MemoryArbiterReader#(type addr);
interface MemArbiterReader#(type addr);
method Action request(addr address);
method Bool grant();
endinterface
// A MemoryArbiter manages concurrent access to memory ports. It
// A MemArbiter manages concurrent access to memory ports. It
// mediates access between 2 writers and 4 readers.
interface MemoryArbiter#(type addr);
interface MemArbiter#(type addr);
// Assigned to port A.
interface MemoryArbiterWriter#(addr) cpu;
interface MemoryArbiterWriter#(addr) debugger;
interface MemoryArbiterReader#(addr) palette;
interface MemArbiterWriter#(addr) cpu;
interface MemArbiterWriter#(addr) debugger;
interface MemArbiterReader#(addr) palette;
// Assigned to port B.
interface MemoryArbiterReader#(addr) tile1;
interface MemoryArbiterReader#(addr) tile2;
interface MemoryArbiterReader#(addr) sprite;
interface MemArbiterReader#(addr) tile1;
interface MemArbiterReader#(addr) tile2;
interface MemArbiterReader#(addr) sprite;
endinterface
// mkMemoryArbiter builds a GARY memory arbiter.
// mkMemArbiter builds a GARY memory arbiter.
//
// Port A arbitrates with strict priority: CPU requests always proceed
// first, followed by debugger requests, then the palette DAC.
//
// Port B does round-robin arbitration, giving each client a fair
// chance of having its requests processed.
module mkMemoryArbiter(MemoryArbiter#(addr) ifc)
module mkMemArbiter(MemArbiter#(addr) ifc)
provisos(Bits#(addr, _),
Eq#(addr),
Alias#(write_req, Tuple2#(Bool, addr)));
@ -143,42 +143,42 @@ module mkMemoryArbiter(MemoryArbiter#(addr) ifc)
//////
// External interface
interface MemoryArbiterWriter cpu;
interface MemArbiterWriter cpu;
method Action request(write, addr);
cpu_req.wset(tuple2(write, addr));
endmethod
method grant = cpu_ok;
endinterface
interface MemoryArbiterWriter debugger;
interface MemArbiterWriter debugger;
method Action request(write, addr);
debugger_req.wset(tuple2(write, addr));
endmethod
method grant = debugger_ok;
endinterface
interface MemoryArbiterReader palette;
interface MemArbiterReader palette;
method Action request(addr);
palette_req.send();
endmethod
method grant = palette_ok;
endinterface
interface MemoryArbiterReader tile1;
interface MemArbiterReader tile1;
method Action request(addr);
portB_req[0].wset(addr);
endmethod
method grant = portB_grant[0];
endinterface
interface MemoryArbiterReader tile2;
interface MemArbiterReader tile2;
method Action request(addr);
portB_req[1].wset(addr);
endmethod
method grant = portB_grant[1];
endinterface
interface MemoryArbiterReader sprite;
interface MemArbiterReader sprite;
method Action request(addr);
portB_req[2].wset(addr);
endmethod

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@ -1,4 +1,4 @@
package MemoryArbiter_Test;
package MemArbiter_Test;
import Assert::*;
import StmtFSM::*;
@ -8,7 +8,7 @@ import List::*;
import Vector::*;
import BuildVector::*;
import MemoryArbiter::*;
import MemArbiter::*;
typedef UInt#(4) Addr;
@ -76,7 +76,7 @@ function TestCase testCase(String name,
endfunction
module mkTB();
MemoryArbiter#(Addr) dut <- mkMemoryArbiter();
MemArbiter#(Addr) dut <- mkMemArbiter();
Vector#(29, TestCase) tests = vec(
testCase("All idle",
@ -205,7 +205,7 @@ module mkTB();
Reg#(UInt#(32)) idx <- mkReg(0);
rule display_test (idx == 0);
$display("RUN TestMemoryArbiter");
$display("RUN TestMemArbiter");
endrule
(* no_implicit_conditions, fire_when_enabled *)
@ -289,7 +289,7 @@ module mkTB();
let next = idx+1;
let max = fromInteger(arrayLength(vectorToArray(tests)));
if (next == max) begin
$display("OK TestMemoryArbiter");
$display("OK TestMemArbiter");
$finish;
end
else