vram: rename MemoryArbiter to something shorter
As I implement the whole transaction-level modeling thing with arbitration, the interface names are getting longer and longer.
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@ -1,6 +1,6 @@
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package Top;
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import MemoryArbiter::*;
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import MemArbiter::*;
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import Vector::*;
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import DReg::*;
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import DelayLine::*;
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@ -30,7 +30,7 @@ module mkTop(Top);
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Vector#(2, Reg#(Maybe#(WriteReq))) wrin <- replicateM(mkDReg(tagged Invalid));
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Vector#(4, Reg#(Maybe#(Addr))) rdin <- replicateM(mkDReg(tagged Invalid));
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MemoryArbiter#(Addr) ret <- mkMemoryArbiter();
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MemArbiter#(Addr) ret <- mkMemArbiter();
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Reg#(Vector#(6, Bool)) ok <- mkReg(replicate(False));
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@ -1,52 +1,52 @@
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package MemoryArbiter;
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package MemArbiter;
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import Vector::*;
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export MemoryArbiterWriter(..);
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export MemoryArbiterReader(..);
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export MemoryArbiter(..);
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export mkMemoryArbiter;
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export MemArbiterWriter(..);
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export MemArbiterReader(..);
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export MemArbiter(..);
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export mkMemArbiter;
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// A MemoryArbiterWriter can request use of a memory port to read or
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// A MemArbiterWriter can request use of a memory port to read or
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// write to an address. When a request is feasible, grant() returns
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// True in the same cycle.
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(* always_ready *)
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interface MemoryArbiterWriter#(type addr);
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interface MemArbiterWriter#(type addr);
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method Action request(Bool write, addr address);
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method Bool grant();
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endinterface
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// MemoryArbiterReader can request use of a memory port to read from
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// MemArbiterReader can request use of a memory port to read from
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// an address. When a request is feasible, grant() returns True in the
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// same cycle.
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(* always_ready *)
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interface MemoryArbiterReader#(type addr);
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interface MemArbiterReader#(type addr);
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method Action request(addr address);
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method Bool grant();
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endinterface
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// A MemoryArbiter manages concurrent access to memory ports. It
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// A MemArbiter manages concurrent access to memory ports. It
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// mediates access between 2 writers and 4 readers.
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interface MemoryArbiter#(type addr);
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interface MemArbiter#(type addr);
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// Assigned to port A.
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interface MemoryArbiterWriter#(addr) cpu;
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interface MemoryArbiterWriter#(addr) debugger;
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interface MemoryArbiterReader#(addr) palette;
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interface MemArbiterWriter#(addr) cpu;
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interface MemArbiterWriter#(addr) debugger;
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interface MemArbiterReader#(addr) palette;
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// Assigned to port B.
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interface MemoryArbiterReader#(addr) tile1;
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interface MemoryArbiterReader#(addr) tile2;
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interface MemoryArbiterReader#(addr) sprite;
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interface MemArbiterReader#(addr) tile1;
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interface MemArbiterReader#(addr) tile2;
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interface MemArbiterReader#(addr) sprite;
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endinterface
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// mkMemoryArbiter builds a GARY memory arbiter.
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// mkMemArbiter builds a GARY memory arbiter.
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//
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// Port A arbitrates with strict priority: CPU requests always proceed
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// first, followed by debugger requests, then the palette DAC.
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//
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// Port B does round-robin arbitration, giving each client a fair
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// chance of having its requests processed.
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module mkMemoryArbiter(MemoryArbiter#(addr) ifc)
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module mkMemArbiter(MemArbiter#(addr) ifc)
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provisos(Bits#(addr, _),
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Eq#(addr),
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Alias#(write_req, Tuple2#(Bool, addr)));
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@ -143,42 +143,42 @@ module mkMemoryArbiter(MemoryArbiter#(addr) ifc)
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//////
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// External interface
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interface MemoryArbiterWriter cpu;
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interface MemArbiterWriter cpu;
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method Action request(write, addr);
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cpu_req.wset(tuple2(write, addr));
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endmethod
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method grant = cpu_ok;
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endinterface
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interface MemoryArbiterWriter debugger;
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interface MemArbiterWriter debugger;
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method Action request(write, addr);
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debugger_req.wset(tuple2(write, addr));
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endmethod
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method grant = debugger_ok;
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endinterface
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interface MemoryArbiterReader palette;
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interface MemArbiterReader palette;
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method Action request(addr);
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palette_req.send();
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endmethod
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method grant = palette_ok;
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endinterface
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interface MemoryArbiterReader tile1;
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interface MemArbiterReader tile1;
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method Action request(addr);
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portB_req[0].wset(addr);
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endmethod
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method grant = portB_grant[0];
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endinterface
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interface MemoryArbiterReader tile2;
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interface MemArbiterReader tile2;
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method Action request(addr);
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portB_req[1].wset(addr);
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endmethod
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method grant = portB_grant[1];
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endinterface
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interface MemoryArbiterReader sprite;
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interface MemArbiterReader sprite;
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method Action request(addr);
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portB_req[2].wset(addr);
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endmethod
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@ -1,4 +1,4 @@
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package MemoryArbiter_Test;
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package MemArbiter_Test;
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import Assert::*;
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import StmtFSM::*;
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@ -8,7 +8,7 @@ import List::*;
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import Vector::*;
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import BuildVector::*;
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import MemoryArbiter::*;
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import MemArbiter::*;
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typedef UInt#(4) Addr;
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@ -76,7 +76,7 @@ function TestCase testCase(String name,
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endfunction
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module mkTB();
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MemoryArbiter#(Addr) dut <- mkMemoryArbiter();
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MemArbiter#(Addr) dut <- mkMemArbiter();
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Vector#(29, TestCase) tests = vec(
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testCase("All idle",
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@ -205,7 +205,7 @@ module mkTB();
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Reg#(UInt#(32)) idx <- mkReg(0);
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rule display_test (idx == 0);
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$display("RUN TestMemoryArbiter");
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$display("RUN TestMemArbiter");
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endrule
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(* no_implicit_conditions, fire_when_enabled *)
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@ -289,7 +289,7 @@ module mkTB();
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let next = idx+1;
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let max = fromInteger(arrayLength(vectorToArray(tests)));
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if (next == max) begin
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$display("OK TestMemoryArbiter");
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$display("OK TestMemArbiter");
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$finish;
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end
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else
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