vram: refactor MemArbiter into separate arbiters

Rather than hardcode one architecture for GARY, the arbiters
are now split and can be allocated per-port. The arbiter interface
includes plumbing so that one arbiter can propagate a write conflict
to another, so it can still implement multi-port arbitration as long
as every client is statically allocated to one port.
This commit is contained in:
David Anderson 2024-09-08 11:42:35 -07:00
parent 2760bad965
commit f31f64f5a2
2 changed files with 396 additions and 379 deletions

View File

@ -3,28 +3,32 @@ package MemArbiter;
import Connectable::*;
import Vector::*;
export MemArbiterWrite(..);
export MemArbiterOp(..);
export MemArbiterServer(..);
export MemArbiterClient(..);
export MemArbiter(..);
export mkMemArbiter;
export MemArbiter(..), mkPriorityMemArbiter, mkRoundRobinMemArbiter;
typedef struct {
Bool write;
addr addr;
} MemArbiterOp#(type addr) deriving (Bits, Eq, FShow);
// A MemArbiterServer receives requests for memory access and emits
// grants.
interface MemArbiterServer#(type request);
method Action request(request req);
interface MemArbiterServer#(type addr);
method Action request(MemArbiterOp#(addr) req);
method Bool grant();
endinterface
// A MemArbiterClient emits requests for memory access and emits
// grants.
interface MemArbiterClient#(type request);
method Maybe#(request) request();
interface MemArbiterClient#(type addr);
method Maybe#(MemArbiterOp#(addr)) request();
method Action grant();
endinterface
instance Connectable#(MemArbiterClient#(req), MemArbiterServer#(req));
module mkConnection(MemArbiterClient#(req) client, MemArbiterServer#(req) server, Empty ifc);
instance Connectable#(MemArbiterClient#(addr), MemArbiterServer#(addr));
module mkConnection(MemArbiterClient#(addr) client, MemArbiterServer#(addr) server, Empty ifc);
rule send_request (client.request matches tagged Valid .req);
server.request(req);
endrule
@ -35,157 +39,149 @@ instance Connectable#(MemArbiterClient#(req), MemArbiterServer#(req));
endmodule
endinstance
typedef struct {
Bool write;
addr addr;
} MemArbiterWrite#(type addr) deriving (Bits, Eq);
// A MemArbiter manages concurrent access to memory ports.
interface MemArbiter#(type addr);
interface MemArbiterServer#(MemArbiterWrite#(addr)) cpu;
interface MemArbiterServer#(MemArbiterWrite#(addr)) debugger;
interface MemArbiterServer#(addr) palette;
interface MemArbiterServer#(addr) tile1;
interface MemArbiterServer#(addr) tile2;
interface MemArbiterServer#(addr) sprite;
interface MemArbiter#(numeric type num_clients, type addr);
interface Vector#(num_clients, MemArbiterServer#(addr)) ports;
method Action forbid_addr(addr addr);
method addr forbidden_addr();
endinterface
// mkMemArbiter builds a GARY memory arbiter.
//
// Port A arbitrates with strict priority: CPU requests go first, then
// the debugger, then the palette DAC.
//
// Port B does round-robin arbitration, giving each client a fair
// share of memory access.
module mkMemArbiter(MemArbiter#(addr))
provisos(Bits#(addr, _),
Eq#(addr),
Alias#(write_req, MemArbiterWrite#(addr)));
module mkPriorityMemArbiter(MemArbiter#(num_clients, addr))
provisos (Bits#(addr, _),
Eq#(addr),
Min#(num_clients, 1, 1));
//////
// Port A users
Vector#(num_clients, RWire#(MemArbiterOp#(addr))) reqs <- replicateM(mkRWire());
Wire#(Vector#(num_clients, Bool)) grants <- mkBypassWire();
RWire#(write_req) cpu_req <- mkRWire();
RWire#(write_req) debugger_req <- mkRWire();
PulseWire palette_req <- mkPulseWire();
RWire#(addr) blocked_in <- mkRWire();
RWire#(addr) blocked_out <- mkRWire();
PulseWire cpu_ok <- mkPulseWire();
PulseWire debugger_ok <- mkPulseWire();
PulseWire palette_ok <- mkPulseWire();
function Bool is_blocked(addr addr);
return blocked_in.wget() == tagged Valid addr;
endfunction
// Address written to by port A, if any. Used to block port B
// clients that are trying to read the same address.
RWire#(addr) written_addr <- mkRWire();
(* no_implicit_conditions, fire_when_enabled *)
rule grant_requests;
Vector#(num_clients, Bool) grant = replicate(False);
Bool done = False;
// We could be fancy with rule conditions to express the priorities
// between clients, but Bluespec has the preempts annotation to
// express the ranking directly.
(* preempts = "grant_cpu, (grant_debugger, grant_palette)" *)
(* preempts = "grant_debugger, grant_palette" *)
(* fire_when_enabled *)
rule grant_cpu (cpu_req.wget matches tagged Valid .req);
cpu_ok.send();
if (req.write)
written_addr.wset(req.addr);
endrule
rule grant_debugger (debugger_req.wget matches tagged Valid .req);
debugger_ok.send();
if (req.write)
written_addr.wset(req.addr);
endrule
rule grant_palette (palette_req);
palette_ok.send();
endrule
//////
// Port B users
Vector#(3, RWire#(addr)) portB_req <- replicateM(mkRWire);
Wire#(Vector#(3, Bool)) portB_grant <- mkBypassWire();
Vector#(3, Bool) init = replicate(False); init[0] = True;
Reg#(Vector#(3, Bool)) priority_vec <- mkReg(init);
rule grant_portB;
Vector#(3, Bool) grants = replicate(False);
Bool port_available = False;
// This algorithm is a little mystifying at first glance, but it
// works. priority_vec has one bool per client, only one of
// which is True. That True bit identifies the client with the
// highest priority on the next request.
//
// This loop goes through each client twice, using
// port_available to track whether a client can grab the port or
// not. When we start iterating, the port is marked unavailable
// until we reach the top priority client, at which point we
// mark the port available and keep scanning. That effectively
// makes the search for a requesting client start at the top
// priority one.
//
// As we loop back around a second time, the availability bool
// gets reset again, but if you take the example of the True bit
// being in the middle of the vector, and consider cases where
// the first requestor is before/after that starting point,
// you'll see that it all works out, and at the end of the loop
// we have a new bit vector where only one client is True - the
// one whose request is granted.
for (Integer i = 0; i < 6; i=i+1) begin
Integer idx = i % 3;
if (priority_vec[idx])
port_available = True;
let req = portB_req[idx].wget();
if (port_available && isValid(req) && req != written_addr.wget()) begin
port_available = False;
grants[idx] = True;
for (Integer i=0; i<valueOf(num_clients); i=i+1) begin
if (reqs[i].wget() matches tagged Valid .req &&& !is_blocked(req.addr) &&& !done) begin
done = True;
grant[i] = True;
if (req.write)
blocked_out.wset(req.addr);
end
end
portB_grant <= grants;
// If we granted a request, the grantee becomes the lowest
// priority client for the next round of requests. If nobody
// requested anything, keep the same priority as before.
if (any(id, grants))
priority_vec <= rotateR(grants);
grants <= grant;
endrule
//////
// External interface
Vector#(num_clients, MemArbiterServer#(addr)) _ifcs = newVector();
for (Integer i=0; i<valueOf(num_clients); i=i+1)
_ifcs[i] = (interface MemArbiterServer#(addr);
method request = reqs[i].wset;
method grant = grants[i];
endinterface);
interface MemArbiterServer cpu;
method request = cpu_req.wset;
method grant = cpu_ok;
endinterface
interface ports = _ifcs;
method forbid_addr = blocked_in.wset;
method addr forbidden_addr() if (blocked_out.wget() matches tagged Valid .addr);
return addr;
endmethod
endmodule
interface MemArbiterServer debugger;
method request = debugger_req.wset;
method grant = debugger_ok;
endinterface
typedef struct {
Bool granted;
Vector#(n, Bool) grant_vec;
UInt#(TLog#(n)) selected;
Maybe#(addr) blocked_addr;
} GrantResult#(numeric type n, type addr) deriving (Bits, Eq, FShow);
interface MemArbiterServer palette;
method Action request(addr);
palette_req.send();
endmethod
method grant = palette_ok;
endinterface
function GrantResult#(n, addr) select_grant(Vector#(n, Maybe#(MemArbiterOp#(addr))) requests,
UInt#(TLog#(n)) lopri,
Maybe#(addr) block_addr)
provisos (Eq#(addr));
interface MemArbiterServer tile1;
method request = portB_req[0].wset;
method grant = portB_grant[0];
endinterface
function is_blocked(addr);
return tagged Valid addr == block_addr;
endfunction
interface MemArbiterServer tile2;
method request = portB_req[1].wset;
method grant = portB_grant[1];
endinterface
function onehot(idx);
let ret = replicate(False);
ret[idx] = True;
return ret;
endfunction
interface MemArbiterServer sprite;
method request = portB_req[2].wset;
method grant = portB_grant[2];
endinterface
function GrantResult#(n, addr) do_fold(GrantResult#(n, addr) acc,
Tuple2#(UInt#(TLog#(n)),
Maybe#(MemArbiterOp#(addr))) next);
match {.idx, .mreq} = next;
if (mreq matches tagged Valid .req &&& !acc.granted &&& !is_blocked(req.addr))
return GrantResult{
granted: True,
grant_vec: onehot(idx),
selected: idx,
blocked_addr: req.write ? tagged Valid req.addr : tagged Invalid
};
else
// Previous grant won, not requesting, or request not satisfiable.
return acc;
endfunction
let in = zip(map(fromInteger, genVector()), requests);
let rot = reverse(rotateBy(reverse(in), lopri));
let seed = GrantResult{
granted: False,
grant_vec: replicate(False),
selected: 0,
blocked_addr: tagged Invalid
};
return foldl(do_fold, seed, rot);
endfunction
module mkRoundRobinMemArbiter(MemArbiter#(num_clients, addr))
provisos (Bits#(addr, _),
Eq#(addr),
Min#(num_clients, 1, 1));
Vector#(num_clients, RWire#(MemArbiterOp#(addr))) reqs <- replicateM(mkRWire);
Wire#(Vector#(num_clients, Bool)) grants <- mkBypassWire();
RWire#(addr) blocked_in <- mkRWire();
Wire#(Maybe#(addr)) blocked_out <- mkBypassWire();
// low_priority is the index of the client that should be last in
// line to receive access. Every time we grant access to a client,
// that client becomes low_priority for the next round.
Reg#(UInt#(TLog#(num_clients))) low_priority <- mkReg(0);
function Maybe#(_t) get_mreq(RWire#(_t) w);
return w.wget();
endfunction
rule grant;
let in = map(get_mreq, reqs);
let res = select_grant(in, low_priority, blocked_in.wget());
grants <= res.grant_vec;
if (res.granted)
low_priority <= res.selected+1;
blocked_out <= res.blocked_addr;
endrule
Vector#(num_clients, MemArbiterServer#(addr)) _ifcs = newVector();
for (Integer i=0; i<valueOf(num_clients); i=i+1)
_ifcs[i] = (interface MemArbiterServer#(addr);
method request = reqs[i].wset;
method grant = grants[i];
endinterface);
interface ports = _ifcs;
method forbid_addr = blocked_in.wset;
method addr forbidden_addr() if (blocked_out matches tagged Valid .addr);
return addr;
endmethod
endmodule
endpackage

View File

@ -14,282 +14,303 @@ typedef UInt#(4) Addr;
typedef struct {
String name;
Maybe#(MemArbiterWrite#(Addr)) cpu;
Maybe#(MemArbiterWrite#(Addr)) debugger;
Maybe#(Addr) palette;
Maybe#(Addr) tile1;
Maybe#(Addr) tile2;
Maybe#(Addr) sprite;
Vector#(6, Bool) want;
} TestCase deriving (Bits, Eq);
Vector#(n, Maybe#(MemArbiterOp#(Addr))) reqs;
Maybe#(Addr) forbid_addr;
function Maybe#(MemArbiterWrite#(Addr)) rwRead(Addr addr);
return tagged Valid MemArbiterWrite{write: False, addr: addr};
Vector#(n, Bool) want_grants;
Maybe#(Addr) want_forbid_addr;
} TestCase#(numeric type n) deriving (Bits, Eq);
function Maybe#(MemArbiterOp#(Addr)) read(Addr addr);
return tagged Valid MemArbiterOp{write: False, addr: addr};
endfunction
function Maybe#(MemArbiterWrite#(Addr)) rwWrite(Addr addr);
return tagged Valid MemArbiterWrite{write: True, addr: addr};
function Maybe#(MemArbiterOp#(Addr)) write(Addr addr);
return tagged Valid MemArbiterOp{write: True, addr: addr};
endfunction
function Maybe#(Addr) read(Addr addr);
return tagged Valid addr;
endfunction
function Maybe#(t) idle();
function Maybe#(MemArbiterOp#(Addr)) idle();
return tagged Invalid;
endfunction
function Vector#(6, Bool) grant(Integer granted_a, Integer granted_b);
let ret = replicate(False);
if (granted_a >= 0)
ret[granted_a] = True;
if (granted_b >= 0)
ret[granted_b+3] = True;
return ret;
function Maybe#(Addr) noForbid();
return tagged Invalid;
endfunction
function TestCase testCase(String name,
Maybe#(MemArbiterWrite#(Addr)) cpu,
Maybe#(MemArbiterWrite#(Addr)) debugger,
Maybe#(Addr) palette,
Maybe#(Addr) tile1,
Maybe#(Addr) tile2,
Maybe#(Addr) sprite,
Integer portA,
Integer portB);
function Maybe#(Addr) forbid(Addr a);
return tagged Valid a;
endfunction
function Vector#(n, Bool) grant(Integer granted);
function gen(idx);
return idx == granted;
endfunction
return genWith(gen);
endfunction
function Vector#(n, Bool) noGrant();
return replicate(False);
endfunction
function TestCase#(n) testCase(String name,
Vector#(n, Maybe#(MemArbiterOp#(Addr))) reqs,
Maybe#(Addr) forbid_addr,
Vector#(n, Bool) want_grants,
Maybe#(Addr) want_forbid_addr);
return TestCase{
name: name,
cpu: cpu,
debugger: debugger,
palette: palette,
tile1: tile1,
tile2: tile2,
sprite: sprite,
want: grant(portA, portB)
reqs: reqs,
forbid_addr: forbid_addr,
want_grants: want_grants,
want_forbid_addr: want_forbid_addr
};
endfunction
module mkTB();
Vector#(29, TestCase) tests = vec(
testCase("All idle",
idle, idle, idle,
idle, idle, idle,
-1, -1),
interface TB;
method Action start();
(* always_ready *)
method Bool done();
endinterface
// Single client accesses at a time
testCase("CPU read", rwRead(1), idle, idle,
idle, idle, idle,
0, -1),
testCase("CPU write", rwWrite(1), idle, idle,
idle, idle, idle,
0, -1),
testCase("Debugger read",
idle, rwRead(1), idle,
idle, idle, idle,
1, -1),
testCase("Debugger write",
idle, rwWrite(1), idle,
idle, idle, idle,
1, -1),
testCase("Palette read",
idle, idle, read(1),
idle, idle, idle,
2, -1),
testCase("Tile1 read",
idle, idle, idle,
read(1), idle, idle,
-1, 0),
testCase("Tile2 read",
idle, idle, idle,
idle, read(1), idle,
-1, 1),
testCase("Sprite read",
idle, idle, idle,
idle, idle, read(1),
-1, 2),
module mkArbiterTB(MemArbiter#(n, Addr) dut, Vector#(m, TestCase#(n)) tests, TB ifc);
let cycles <- mkCycleCounter();
// Strict priority on port A
testCase("CPU + Debugger + Palette",
rwRead(1), rwRead(2), read(3),
idle, idle, idle,
0, -1),
testCase("CPU + Palette",
rwRead(1), idle, read(3),
idle, idle, idle,
0, -1),
testCase("Debugger + Palette",
idle, rwRead(2), read(3),
idle, idle, idle,
1, -1),
Reg#(Bit#(TLog#(m))) idx <- mkReg(0);
Reg#(Bool) running <- mkReg(False);
// Round-robin on port B
testCase("Sprite read", // to reset round robin
idle, idle, idle,
idle, idle, read(1),
-1, 2),
testCase("Tile1 + Tile2 + Sprite",
idle, idle, idle,
read(1), read(2), read(3),
-1, 0),
testCase("Tile1 + Tile2 + Sprite",
idle, idle, idle,
read(1), read(2), read(3),
-1, 1),
testCase("Tile1 + Tile2 + Sprite",
idle, idle, idle,
read(1), read(2), read(3),
-1, 2),
testCase("Tile1 + Tile2 + Sprite",
idle, idle, idle,
read(1), read(2), read(3),
-1, 0),
testCase("Tile1 + Sprite",
idle, idle, idle,
read(1), idle, read(3),
-1, 2),
testCase("Tile2 + Sprite",
idle, idle, idle,
idle, read(2), read(3),
-1, 1),
testCase("Tile2 + Sprite",
idle, idle, idle,
idle, read(2), read(3),
-1, 2),
// Inter-port conflicts
testCase("Read/read, no conflict",
rwRead(0), idle, idle,
read(0), idle, idle,
0, 0),
testCase("Write/read, no conflict",
rwWrite(1), idle, idle,
read(0), idle, idle,
0, 0),
testCase("Tile1 write conflict",
rwWrite(0), idle, idle,
read(0), idle, idle,
0, -1),
testCase("Tile2 write conflict",
rwWrite(0), idle, idle,
idle, read(0), idle,
0, -1),
testCase("Sprite write conflict",
rwWrite(0), idle, idle,
idle, idle, read(0),
0, -1),
testCase("Tile1 write conflict with debugger",
idle, rwWrite(0), idle,
read(0), idle, idle,
1, -1),
testCase("Sprite read", // to reset round robin
idle, idle, idle,
idle, idle, read(1),
-1, 2),
testCase("CPU write conflict, other port feasible",
rwWrite(0), idle, idle,
read(0), read(1), idle,
0, 1),
testCase("CPU write conflict, conflict resolved",
idle, idle, idle,
read(0), idle, idle,
-1, 0));
MemArbiter#(Addr) dut <- mkMemArbiter();
Reg#(UInt#(32)) idx <- mkReg(0);
rule display_test (idx == 0);
$display("RUN TestMemArbiter");
endrule
for (Integer i=0; i<valueOf(n); i=i+1) begin
rule request (running && isValid(tests[idx].reqs[i]));
dut.ports[i].request(validValue(tests[idx].reqs[i]));
endrule
end
(* no_implicit_conditions, fire_when_enabled *)
rule input_cpu (tests[idx].cpu matches tagged Valid .req);
dut.cpu.request(req);
rule forbid (running && isValid(tests[idx].forbid_addr));
dut.forbid_addr(validValue(tests[idx].forbid_addr));
endrule
(* no_implicit_conditions, fire_when_enabled *)
rule input_debugger (tests[idx].debugger matches tagged Valid .req);
dut.debugger.request(req);
Wire#(Maybe#(Addr)) got_forbid_addr <- mkDWire(tagged Invalid);
(* fire_when_enabled *)
rule collect_forbid (running);
got_forbid_addr <= tagged Valid dut.forbidden_addr();
endrule
(* no_implicit_conditions, fire_when_enabled *)
rule input_palette (tests[idx].palette matches tagged Valid .addr);
dut.palette.request(addr);
endrule
(* no_implicit_conditions, fire_when_enabled *)
rule input_tile1 (tests[idx].tile1 matches tagged Valid .addr);
dut.tile1.request(addr);
endrule
(* no_implicit_conditions, fire_when_enabled *)
rule input_tile2 (tests[idx].tile2 matches tagged Valid .addr);
dut.tile2.request(addr);
endrule
(* no_implicit_conditions, fire_when_enabled *)
rule input_sprite (tests[idx].sprite matches tagged Valid .addr);
dut.sprite.request(addr);
endrule
function Fmt rw_str(Maybe#(MemArbiterWrite#(Addr)) v);
function Fmt req_s(Maybe#(MemArbiterOp#(Addr)) v);
case (v) matches
tagged Valid .req: begin
if (req.write)
return $format("Write(%0d)", req.addr);
else
return $format("Read(%0d) ", req.addr);
end
tagged Invalid: return $format("Idle ");
tagged Invalid: return $format("Idle");
tagged Valid .req &&& req.write: return $format("Write(%0d)", req.addr);
tagged Valid .req: return $format("Read(%0d)", req.addr);
endcase
endfunction
function Fmt ro_str(Maybe#(Addr) v);
function Fmt addr_s(Maybe#(Addr) v);
case (v) matches
tagged Valid .addr: return $format("Read(%0d) ", addr);
tagged Invalid: return $format("Idle ");
tagged Invalid: return $format("<nil>");
tagged Valid .a: return $format("%0d", a);
endcase
endfunction
(* no_implicit_conditions, fire_when_enabled *)
rule check_grants;
Vector#(6, Bool) gotVec = newVector;
gotVec[0] = dut.cpu.grant();
gotVec[1] = dut.debugger.grant();
gotVec[2] = dut.palette.grant();
gotVec[3] = dut.tile1.grant();
gotVec[4] = dut.tile2.grant();
gotVec[5] = dut.sprite.grant();
rule check (running);
let test = tests[idx];
let got = pack(reverse(gotVec));
let want = pack(reverse(test.want));
let reqs = test.reqs;
let want_grants = test.want_grants;
let want_forbid_addr = test.want_forbid_addr;
Vector#(n, Bool) got_grants = newVector;
for (Integer i=0; i<valueOf(n); i=i+1)
got_grants[i] = dut.ports[i].grant();
$display("RUN %s (%0d)", test.name, idx+1);
if (got != want) begin
$display(" input: ",
"0:", rw_str(test.cpu), " 1:", rw_str(test.debugger), " 2:", ro_str(test.palette),
" 3:", ro_str(test.tile1), " 4:", ro_str(test.tile2), " 5:", ro_str(test.sprite));
$display(" got : %03b %03b", got[5:3], got[2:0]);
$display(" want : %03b %03b", want[5:3], want[2:0]);
dynamicAssert(got == want, "wrong arbiter output");
$display("RUN %s (%0d)", tests[idx].name, idx);
if (got_grants != want_grants || got_forbid_addr != want_forbid_addr) begin
$display(" input:");
for (Integer i=0; i<valueOf(n); i=i+1)
$display(" ", $format("%0d", i), ": ", req_s(reqs[i]));
$display(" forbid: ", addr_s(test.forbid_addr));
$display(" output:");
$display(" grants: ", fshow(got_grants));
$display(" forbid: ", addr_s(got_forbid_addr));
$display(" want grants: ", fshow(tests[idx].want_grants));
$display(" want forbid: ", addr_s(want_forbid_addr));
dynamicAssert(False, "wrong arbiter output");
end
dynamicAssert(cycles == 1, "arbiter took more than 0 cycles");
$display("OK %s", tests[idx].name);
cycles.reset();
if (idx == fromInteger(valueOf(m)-1))
running <= False;
else
$display("OK %s", test.name);
idx <= idx+1;
endrule
(* no_implicit_conditions, fire_when_enabled *)
rule advance_test;
let next = idx+1;
let max = fromInteger(arrayLength(vectorToArray(tests)));
if (next == max) begin
$display("OK TestMemArbiter");
$finish;
end
else
idx <= next;
endrule
method Action start() if (!running && idx == 0);
cycles.reset();
running <= True;
endmethod
method Bool done();
return !running && idx != 0;
endmethod
endmodule
module mkTB(Empty);
///////////////////////////////
// Strict arbiter
let strictTests = vec(
// Simple grants
testCase("All idle",
vec(idle, idle, idle), noForbid,
noGrant, noForbid),
testCase("Port 0 read",
vec(read(1), idle, idle), noForbid,
grant(0), noForbid),
testCase("Port 0 write",
vec(write(1), idle, idle), noForbid,
grant(0), forbid(1)),
testCase("Port 1 read",
vec(idle, read(1), idle), noForbid,
grant(1), noForbid),
testCase("Port 1 write",
vec(idle, write(1), idle), noForbid,
grant(1), forbid(1)),
testCase("Port 2 read",
vec(idle, idle, read(1)), noForbid,
grant(2), noForbid),
testCase("Port 2 write",
vec(idle, idle, write(1)), noForbid,
grant(2), forbid(1)),
// Priorities
testCase("Port 0+1",
vec(read(1), read(2), idle), noForbid,
grant(0), noForbid),
testCase("Port 0+2",
vec(read(1), idle, read(2)), noForbid,
grant(0), noForbid),
testCase("Port 1+2",
vec(idle, read(1), read(2)), noForbid,
grant(1), noForbid),
testCase("Port 0+1+2",
vec(read(1), read(2), read(3)), noForbid,
grant(0), noForbid),
testCase("Port 0+1+2, overruled writes",
vec(read(1), write(1), write(2)), noForbid,
grant(0), noForbid),
// Forbidden addrs
testCase("Port 0 read denied",
vec(read(1), read(2), idle), forbid(1),
grant(1), noForbid),
testCase("Port 0 write denied",
vec(write(1), read(2), idle), forbid(1),
grant(1), noForbid),
testCase("Port 0 no addr match",
vec(write(2), idle, idle), forbid(1),
grant(0), forbid(2)),
testCase("Port 0 denied, no alternatives",
vec(write(1), idle, idle), forbid(1),
noGrant, noForbid)
);
MemArbiter#(3, Addr) strict <- mkPriorityMemArbiter();
let strictTB <- mkArbiterTB(strict, strictTests);
///////////////////////////////
// Round-robin arbiter
let rrTests = vec(
// Simple grants
testCase("All idle",
vec(idle, idle, idle), noForbid,
noGrant, noForbid),
testCase("Port 0 read",
vec(read(1), idle, idle), noForbid,
grant(0), noForbid),
testCase("Port 0 write",
vec(write(1), idle, idle), noForbid,
grant(0), forbid(1)),
testCase("Port 1 read",
vec(idle, read(1), idle), noForbid,
grant(1), noForbid),
testCase("Port 1 write",
vec(idle, write(1), idle), noForbid,
grant(1), forbid(1)),
testCase("Port 2 read",
vec(idle, idle, read(1)), noForbid,
grant(2), noForbid),
testCase("Port 2 write",
vec(idle, idle, write(1)), noForbid,
grant(2), forbid(1)),
// Priorities
testCase("Port 2 to reset RR",
vec(idle, idle, read(1)), noForbid,
grant(2), noForbid),
testCase("Port 0+1 #1",
vec(read(1), read(2), idle), noForbid,
grant(0), noForbid),
testCase("Port 0+1 #2",
vec(read(1), read(2), idle), noForbid,
grant(1), noForbid),
testCase("Port 0+1 #3",
vec(read(1), read(2), idle), noForbid,
grant(0), noForbid),
testCase("Port 0+2 #1",
vec(read(1), idle, read(2)), noForbid,
grant(2), noForbid),
testCase("Port 0+2 #2",
vec(read(1), idle, read(2)), noForbid,
grant(0), noForbid),
testCase("Port 0+1+2 #1",
vec(read(1), read(2), read(3)), noForbid,
grant(1), noForbid),
testCase("Port 0+1+2 #2",
vec(read(1), read(2), read(3)), noForbid,
grant(2), noForbid),
testCase("Port 0+1+2 #3",
vec(read(1), read(2), read(3)), noForbid,
grant(0), noForbid),
testCase("Port 0+1+2 #4",
vec(read(1), read(2), read(3)), noForbid,
grant(1), noForbid),
// Forbidden addrs
testCase("Port 2 to reset RR",
vec(idle, idle, read(1)), noForbid,
grant(2), noForbid),
testCase("RR with denied writes #1",
vec(read(1), write(2), read(3)), forbid(3),
grant(0), noForbid),
testCase("RR with denied writes #2",
vec(read(1), write(2), read(3)), forbid(3),
grant(1), forbid(2)),
testCase("RR with denied writes #3",
vec(read(1), write(2), read(3)), forbid(3),
grant(0), noForbid),
testCase("RR with denied writes #4",
vec(read(1), write(2), read(3)), forbid(3),
grant(1), forbid(2))
);
MemArbiter#(3, Addr) rr <- mkRoundRobinMemArbiter();
let rrTB <- mkArbiterTB(rr, rrTests);
runTest(100,
mkTest("MemArbiter", seq
mkTest("MemArbiter/Strict", seq
strictTB.start();
await(strictTB.done);
endseq);
mkTest("MemArbiter/RoundRobin", seq
rrTB.start();
await(rrTB.done);
endseq);
endseq));
endmodule
endpackage