sentinel65x: start of Sentinel 65X top-level glue, with a PLL module
The PLL generates a 100MHz clock for GARY, 10MHz for the CPU and system bus, and 25MHz for VGA out.
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package PLL;
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// Frequencies: FPGA 100MHz, CPU 10MHz, VGA 25MHz
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//
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// To regenerate, see 'inv genclk -h'
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// Clocks are the various clocks used in GARY.
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interface Clocks;
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// main_clk is the internal clock that most of the design runs at.
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interface Clock main_clk;
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// cpu_clk is the clock generated and output for use by the 65X
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// CPU. The system bus interface is clocked by cpu_clk.
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interface Clock cpu_clk;
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// vga_clk is the pixel clock for the video output.
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interface Clock vga_clk;
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// locked is whether the PLL has locked and is producing stable
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// clocks.
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//
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// TODO: hook this into clock gating or global reset, to hold the
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// FPGA in a safe state while the PLL starts up and locks.
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(* always_ready *)
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method Bool locked();
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endinterface
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// mkPLL takes in a reference clock signal and generates GARY's
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// clocks. All the output clocks are in phase with main_clk,
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// i.e. every posedge of cpu_clk and vga_clk is also a posedge of
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// main_clk.
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import "BVI" PLL =
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module mkPLL(Clock clk, Clocks ifc);
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default_clock no_clock;
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default_reset no_reset;
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input_clock ref_clk(CLK_REF, (* unused *)CLK_REF_GATE) = clk;
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output_clock main_clk(CLK_MAIN);
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output_clock cpu_clk(CLK_CPU);
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output_clock vga_clk(CLK_VGA);
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ancestor(cpu_clk, main_clk);
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ancestor(vga_clk, main_clk);
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method locked locked();
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schedule locked CF locked;
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endmodule
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endpackage
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@ -0,0 +1,60 @@
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// diamond 3.7 accepts this PLL
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// diamond 3.8-3.9 is untested
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// diamond 3.10 or higher is likely to abort with error about unable to use feedback signal
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// cause of this could be from wrong CPHASE/FPHASE parameters
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module PLL
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(
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input CLK_REF, // 25 MHz, 0 deg
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output CLK_MAIN, // 100 MHz, 0 deg
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output CLK_CPU, // 10 MHz, 0 deg
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output CLK_VGA, // 25 MHz, 0 deg
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output locked
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);
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(* FREQUENCY_PIN_CLKI="25" *)
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(* FREQUENCY_PIN_CLKOP="100" *)
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(* FREQUENCY_PIN_CLKOS="10" *)
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(* FREQUENCY_PIN_CLKOS2="25" *)
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(* ICP_CURRENT="12" *) (* LPF_RESISTOR="8" *) (* MFG_ENABLE_FILTEROPAMP="1" *) (* MFG_GMCREF_SEL="2" *)
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EHXPLLL #(
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.PLLRST_ENA("DISABLED"),
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.INTFB_WAKE("DISABLED"),
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.STDBY_ENABLE("DISABLED"),
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.DPHASE_SOURCE("DISABLED"),
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.OUTDIVIDER_MUXA("DIVA"),
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.OUTDIVIDER_MUXB("DIVB"),
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.OUTDIVIDER_MUXC("DIVC"),
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.OUTDIVIDER_MUXD("DIVD"),
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.CLKI_DIV(1),
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.CLKOP_ENABLE("ENABLED"),
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.CLKOP_DIV(6),
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.CLKOP_CPHASE(2),
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.CLKOP_FPHASE(0),
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.CLKOS_ENABLE("ENABLED"),
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.CLKOS_DIV(60),
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.CLKOS_CPHASE(2),
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.CLKOS_FPHASE(0),
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.CLKOS2_ENABLE("ENABLED"),
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.CLKOS2_DIV(24),
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.CLKOS2_CPHASE(2),
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.CLKOS2_FPHASE(0),
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.FEEDBK_PATH("CLKOP"),
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.CLKFB_DIV(4)
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) pll_i (
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.RST(1'b0),
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.STDBY(1'b0),
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.CLKI(CLK_REF),
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.CLKOP(CLK_MAIN),
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.CLKOS(CLK_CPU),
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.CLKOS2(CLK_VGA),
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.CLKFB(CLK_MAIN),
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.CLKINTFB(),
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.PHASESEL0(1'b0),
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.PHASESEL1(1'b0),
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.PHASEDIR(1'b1),
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.PHASESTEP(1'b1),
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.PHASELOADREG(1'b1),
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.PLLWAKESYNC(1'b0),
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.ENCLKOP(1'b0),
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.LOCK(locked)
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);
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endmodule
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18
tasks.py
18
tasks.py
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@ -202,3 +202,21 @@ def test(c, target):
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def clean(c):
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if Path("out").is_dir():
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shutil.rmtree("out")
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@task
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def genclk(c, in_mhz=25, main_mhz=100, cpu_mhz=10, vga_mhz=25):
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out = Path("gary/PLL.v")
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c.run(f"ecppll -f {out} --module PLL --clkin_name CLK_REF --clkin {in_mhz} --clkout0_name CLK_MAIN --clkout0 {main_mhz} --clkout1_name CLK_CPU --clkout1 {cpu_mhz} --clkout2_name CLK_VGA --clkout2 {vga_mhz}")
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bsv_out = out.with_suffix(".bsv")
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with open(bsv_out) as f:
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lines = f.readlines()
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idx = None
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for i, l in enumerate(lines):
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if l.startswith("// Frequencies: "):
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idx = i
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break
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if idx is None:
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print(f"WARNING: couldn't find frequencies line in {bsv_out}, not updating")
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lines[i] = f"// Frequencies: FPGA {main_mhz}MHz, CPU {cpu_mhz}MHz, VGA {vga_mhz}MHz\n"
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with open(bsv_out, "w") as f:
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f.write("".join(lines))
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