vram/VRAM: early VRAM implementation
Only checked up to mkByteRAMArray, main VRAM still WIP
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package Top;
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import VRAM::*;
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import ECP5_RAM::*;
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import TriState::*;
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(* always_enabled *)
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interface Top;
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method Action phi2(bit v);
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method Action we(bit we);
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method Action addr(UInt#(24) addr);
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interface InOut#(Bit#(8)) data();
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endinterface
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(* synthesize *)
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module mkTop(Top);
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Reg#(PortReq) reqA <- mkRegU();
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Reg#(VRAMData) respA <- mkRegU();
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let _ret <- mkByteRAMArray(8);
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rule putA;
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_ret.portA.put(reqA.chip_select, reqA.write, reqA.addr, reqA.datain);
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endrule
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rule getA;
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respA <= _ret.portA.read();
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endrule
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method portA_read = respA._read;
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method Action portA_put(cs, w, a, d);
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reqA <= PortReq{chip_select: cs, write: w, addr: a, datain: d};
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endmethod
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method portB_read = _ret.portB.read;
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method portB_put = _ret.portB.put;
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endmodule
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endpackage
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package VRAM;
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import GetPut::*;
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import ClientServer::*;
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import DReg::*;
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import BRAM::*;
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import Vector::*;
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import FIFOF::*;
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import SpecialFIFOs::*;
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import DelayLine::*;
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import ECP5_RAM::*;
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typedef UInt#(17) VRAMAddr;
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typedef Bit#(8) VRAMData;
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// Each byte RAM we build below can address 4096 bytes, which is 12
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// address bits.
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typedef UInt#(12) ByteAddr;
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// The difference between ByteRAM_Addr and VRAMAddr is the chip
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// select ID.
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typedef UInt#(5) ChipAddr;
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// ByteRAM is two EBRs glued together to make a whole-byte memory.
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typedef EBR#(ByteAddr, VRAMData, ByteAddr, VRAMData) ByteRAM;
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// mkByteRAM glues two ECP5 EBRs together to make a 4096x8b memory
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// block. Like the underlying ECP5 EBRs, callers must bring their own
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// flow control to read out responses one cycle after putting a read
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// request.
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module mkByteRAM(UInt#(3) chip_addr, ByteRAM ifc);
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EBRPortConfig cfg = defaultValue;
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cfg.chip_select_addr = chip_addr;
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EBR#(ByteAddr, Bit#(4), ByteAddr, Bit#(4)) upper <- mkEBRCore(cfg, cfg);
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EBR#(ByteAddr, Bit#(4), ByteAddr, Bit#(4)) lower <- mkEBRCore(cfg, cfg);
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interface EBRPort portA;
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method Action put(UInt#(3) chip_select, Bool write, ByteAddr addr, VRAMData data_in);
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upper.portA.put(chip_select, write, addr, truncate(data_in>>4));
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lower.portA.put(chip_select, write, addr, truncate(data_in));
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endmethod
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method VRAMData read();
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return (extend(upper.portA.read())<<4) | (extend(lower.portA.read()));
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endmethod
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endinterface
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interface EBRPort portB;
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method Action put(UInt#(3) chip_select, Bool write, ByteAddr addr, VRAMData data_in);
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upper.portB.put(chip_select, write, addr, truncate(data_in>>4));
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lower.portB.put(chip_select, write, addr, truncate(data_in));
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endmethod
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method VRAMData read();
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return (extend(upper.portB.read())<<4) | (extend(lower.portB.read()));
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endmethod
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endinterface
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endmodule : mkByteRAM
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module mkByteRAMArray(Integer num_chips, ByteRAM ifc);
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if (num_chips > 8)
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error("mkByteRAMArray can only array 8 raw ByteRAMs");
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ByteRAM blocks[num_chips];
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for (Integer i=0; i<num_chips; i=i+1)
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blocks[i] <- mkByteRAM(fromInteger(i));
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DelayLine#(UInt#(3)) read_chip_A <- mkDelayLine(1);
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DelayLine#(UInt#(3)) read_chip_B <- mkDelayLine(1);
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interface EBRPort portA;
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method Action put(UInt#(3) chip_select, Bool write, ByteAddr addr, VRAMData data_in);
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for (Integer i=0; i<num_chips; i=i+1)
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blocks[i].portA.put(chip_select, write, addr, data_in);
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if (write)
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read_chip_A <= chip_select;
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endmethod
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method VRAMData read();
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if (read_chip_A.ready)
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if (read_chip_A <= fromInteger(num_chips-1))
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return blocks[read_chip_A].portA.read();
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else
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return 0;
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else
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return 0;
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endmethod
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endinterface
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interface EBRPort portB;
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method Action put(UInt#(3) chip_select, Bool write, ByteAddr addr, VRAMData data_in);
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for (Integer i=0; i<num_chips; i=i+1)
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blocks[i].portB.put(chip_select, write, addr, data_in);
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if (write)
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read_chip_B <= chip_select;
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endmethod
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method VRAMData read();
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if (read_chip_B.ready)
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if (read_chip_B <= fromInteger(num_chips-1))
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return blocks[read_chip_B].portB.read();
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else
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return 0;
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else
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return 0;
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endmethod
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endinterface
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endmodule
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typedef struct {
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VRAMAddr addr;
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Maybe#(VRAMData) data;
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} VRAMRequest deriving (Bits, Eq);
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typedef struct {
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VRAMData data;
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} VRAMResponse deriving (Bits, Eq);
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typedef Server#(VRAMRequest, VRAMResponse) VRAMServer;
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typedef Client#(VRAMRequest, VRAMResponse) VRAMClient;
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interface VRAM;
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interface VRAMServer portA;
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interface VRAMServer portB;
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endinterface
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module mkVRAM(Integer num_4kB_blocks, VRAM ifc);
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if (num_4kB_blocks > 32)
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error("maximum number of blocks is 32 (128KiB)");
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UInt#(TAdd#(SizeOf#(VRAMAddr), 1)) max_request_addr = fromInteger((4096 * num_4kB_blocks));
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function Tuple2#(ChipAddr, ByteAddr) split_addr(VRAMAddr a);
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UInt#(TAdd#(SizeOf#(VRAMAddr), 1)) expanded = extend(a);
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VRAMAddr wrapped = truncate(expanded % max_request_addr);
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match {.chip, .off} = split(pack(wrapped));
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return tuple2(unpack(chip), unpack(off));
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endfunction
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ByteRAM blocks[num_4kB_blocks];
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for (Integer i=0; i<num_4kB_blocks; i=i+1)
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blocks[i] <- mkByteRAM(0);
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Reg#(Maybe#(ChipAddr)) inflight_A[2] <- mkCReg(2, tagged Invalid);
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Reg#(Maybe#(ChipAddr)) inflight_B[2] <- mkCReg(2, tagged Invalid);
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interface VRAMServer portA;
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interface Put request;
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method Action put(VRAMRequest req) if (inflight_A[1] matches tagged Invalid);
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match {.chip, .off} = split_addr(req.addr);
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blocks[chip].portA.put(0, isValid(req.data), off, fromMaybe(0, req.data));
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if (!isValid(req.data))
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inflight_A[1] <= tagged Valid chip;
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endmethod
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endinterface
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interface Get response;
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method ActionValue#(VRAMResponse) get() if (inflight_A[0] matches tagged Valid .chip);
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inflight_A[0] <= tagged Invalid;
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return VRAMResponse{data: blocks[chip].portA.read()};
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endmethod
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endinterface
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endinterface
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interface VRAMServer portB;
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interface Put request;
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method Action put(VRAMRequest req) if (inflight_B[1] matches tagged Invalid);
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match {.chip, .off} = split_addr(req.addr);
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blocks[chip].portB.put(0, isValid(req.data), off, fromMaybe(0, req.data));
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if (!isValid(req.data))
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inflight_B[1] <= tagged Valid chip;
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endmethod
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endinterface
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interface Get response;
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method ActionValue#(VRAMResponse) get() if (inflight_B[0] matches tagged Valid .chip);
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inflight_B[0] <= tagged Invalid;
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return VRAMResponse{data: blocks[chip].portB.read()};
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endmethod
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endinterface
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endinterface
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endmodule
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endpackage
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