Graphics Adapter for Retropixel Yeeting. An experiment for now, who knows what might happen.

David Anderson 930f9f7078 sentinel65x: start of Sentinel 65X top-level glue, with a PLL module ... The PLL generates a 100MHz clock for GARY, 10MHz for the CPU and system bus, and 25MHz for VGA out.		2024-09-06 16:21:25 -07:00
experiments	vram/VRAM: early VRAM implementation	2024-09-06 16:11:55 -07:00
images	Add tentative requirements document to capture requests.	2024-08-14 09:39:42 -07:00
lib	tasks: support running nextpnr with a generic ulx3s pin map	2024-09-06 16:11:03 -07:00
sentinel65x	sentinel65x: start of Sentinel 65X top-level glue, with a PLL module	2024-09-06 16:21:25 -07:00
sim	Add some early testing harness for the sim DP16KD	2024-08-30 22:14:10 -07:00
vram	vram/VRAM: early VRAM implementation	2024-09-06 16:11:55 -07:00
.gitignore	add a simple build/test script	2024-08-14 09:39:42 -07:00
.svlint.toml	Add svlint config	2024-08-23 00:21:15 -07:00
LICENSE	Initial basic files	2024-08-13 22:24:20 -07:00
Requirements.md	Requirements.md: fix image insertion syntax	2024-08-14 09:44:14 -07:00
flake.lock	Initial basic files	2024-08-13 22:24:20 -07:00
flake.nix	sim: implementation of a simulation model DP16KD	2024-08-30 18:54:54 -07:00
tasks.py	sentinel65x: start of Sentinel 65X top-level glue, with a PLL module	2024-09-06 16:21:25 -07:00