tasks.py: fix typo in synth process

2024-09-07 16:00:45 -07:00 · 2024-09-07 16:00:45 -07:00 · dd551ce09b
parent fc4b212139
commit dd551ce09b
1 changed files with 1 additions and 1 deletions
--- a/tasks.py
+++ b/tasks.py
@ -50,7 +50,7 @@ def find_verilog_modules(c, target_dir, modules):
        module_path = None
        verilog_path = Path(module).with_suffix(".v")
        # Try preferred libpaths first.
-        for p in libpaths:
+        for p in preferred_libpaths:
            f = p / verilog_path
            if f.is_file():
                module_path = f