From dd551ce09b5121f42c714c6582060b6e0bd3d526 Mon Sep 17 00:00:00 2001 From: David Anderson Date: Sat, 7 Sep 2024 16:00:45 -0700 Subject: [PATCH] tasks.py: fix typo in synth process --- tasks.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/tasks.py b/tasks.py index 78627e9..7dd003f 100644 --- a/tasks.py +++ b/tasks.py @@ -50,7 +50,7 @@ def find_verilog_modules(c, target_dir, modules): module_path = None verilog_path = Path(module).with_suffix(".v") # Try preferred libpaths first. - for p in libpaths: + for p in preferred_libpaths: f = p / verilog_path if f.is_file(): module_path = f