experiments/primitive_ram: clean up old testing code
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@ -10,8 +10,6 @@ interface Top;
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method Action putB((* port="flash_csn" *) Bool write, (* port="audio_l" *) Bit#(4) addr, (* port="audio_r" *) Bit#(4) data);
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(* result="led" *)
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method Bit#(8) read();
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//interface EBRPort#(Bit#(12), Bit#(4)) ram1;
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//interface EBRPort#(Bit#(12), Bit#(4)) ram2;
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endinterface
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(* synthesize,clock_prefix="clk_25mhz",reset_prefix="audio_v" *)
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@ -20,8 +18,6 @@ module mkTop(Top ifc);
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cfgA.write_mode = Normal;
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cfgA.chip_select_addr = 5;
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EBRPortConfig cfgB = defaultValue;
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// cfgB.clk = tagged Valid clk2;
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// cfgB.rstN = tagged Valid rst2;
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cfgB.register_output = True;
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let r <- mkEBR(cfgA, cfgB);
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@ -40,8 +36,6 @@ module mkTop(Top ifc);
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method Bit#(8) read();
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return out;
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endmethod
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//interface EBRPort ram1 = r.portA;
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//interface EBRPort ram2 = r.portB;
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endmodule
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endpackage
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