From f61328dac42b83d1d2a7e7f16bcee5b8e6eec121 Mon Sep 17 00:00:00 2001
From: David Anderson <dave@natulte.net>
Date: Fri, 6 Sep 2024 16:23:47 -0700
Subject: [PATCH] experiments/primitive_ram: clean up old testing code

---
 experiments/primitive_ram/Top.bsv | 6 ------
 1 file changed, 6 deletions(-)

diff --git a/experiments/primitive_ram/Top.bsv b/experiments/primitive_ram/Top.bsv
index 580ed9b..41ae1c4 100644
--- a/experiments/primitive_ram/Top.bsv
+++ b/experiments/primitive_ram/Top.bsv
@@ -10,8 +10,6 @@ interface Top;
    method Action putB((* port="flash_csn" *) Bool write, (* port="audio_l" *) Bit#(4) addr, (* port="audio_r" *) Bit#(4) data);
    (* result="led" *)
    method Bit#(8) read();
-   //interface EBRPort#(Bit#(12), Bit#(4)) ram1;
-   //interface EBRPort#(Bit#(12), Bit#(4)) ram2;
 endinterface
 
 (* synthesize,clock_prefix="clk_25mhz",reset_prefix="audio_v" *)
@@ -20,8 +18,6 @@ module mkTop(Top ifc);
    cfgA.write_mode = Normal;
    cfgA.chip_select_addr = 5;
    EBRPortConfig cfgB = defaultValue;
-   // cfgB.clk = tagged Valid clk2;
-   // cfgB.rstN = tagged Valid rst2;
    cfgB.register_output = True;
    let r <- mkEBR(cfgA, cfgB);
 
@@ -40,8 +36,6 @@ module mkTop(Top ifc);
    method Bit#(8) read();
       return out;
    endmethod
-   //interface EBRPort ram1 = r.portA;
-   //interface EBRPort ram2 = r.portB;
 endmodule
 
 endpackage