vram: one more arbiter test for port conflicts
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5e22d03e15
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@ -78,7 +78,7 @@ endfunction
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module mkTB();
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MemoryArbiter#(Addr) dut <- mkMemoryArbiter();
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Vector#(26, TestCase) tests = vec(
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Vector#(29, TestCase) tests = vec(
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testCase("All idle",
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idle, idle, idle,
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idle, idle, idle,
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@ -164,6 +164,7 @@ module mkTB();
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idle, read(2), read(3),
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-1, 2),
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// Inter-port conflicts
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testCase("Read/read, no conflict",
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rwRead(0), idle, idle,
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read(0), idle, idle,
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@ -187,7 +188,19 @@ module mkTB();
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testCase("Tile1 write conflict with debugger",
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idle, rwWrite(0), idle,
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read(0), idle, idle,
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1, -1)
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1, -1),
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testCase("Sprite read", // to reset round robin
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idle, idle, idle,
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idle, idle, read(1),
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-1, 2),
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testCase("CPU write conflict, other port feasible",
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rwWrite(0), idle, idle,
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read(0), read(1), idle,
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0, 1),
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testCase("CPU write conflict, conflict resolved",
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idle, idle, idle,
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read(0), idle, idle,
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-1, 0)
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);
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