From 60348fefd2056a206a6a781f24c383e48558514f Mon Sep 17 00:00:00 2001
From: David Anderson <dave@natulte.net>
Date: Sat, 31 Aug 2024 13:25:04 -0700
Subject: [PATCH] vram: one more arbiter test for port conflicts

---
 vram/MemoryArbiter_Test.bsv | 17 +++++++++++++++--
 1 file changed, 15 insertions(+), 2 deletions(-)

diff --git a/vram/MemoryArbiter_Test.bsv b/vram/MemoryArbiter_Test.bsv
index 59971bf..59e0071 100644
--- a/vram/MemoryArbiter_Test.bsv
+++ b/vram/MemoryArbiter_Test.bsv
@@ -78,7 +78,7 @@ endfunction
 module mkTB();
    MemoryArbiter#(Addr) dut <- mkMemoryArbiter();
 
-   Vector#(26, TestCase) tests = vec(
+   Vector#(29, TestCase) tests = vec(
       testCase("All idle",
                idle, idle, idle,
                idle, idle, idle,
@@ -164,6 +164,7 @@ module mkTB();
                idle, read(2), read(3),
                -1, 2),
 
+      // Inter-port conflicts
       testCase("Read/read, no conflict",
                rwRead(0), idle, idle,
                read(0), idle, idle,
@@ -187,7 +188,19 @@ module mkTB();
       testCase("Tile1 write conflict with debugger",
                idle, rwWrite(0), idle,
                read(0), idle, idle,
-               1, -1)
+               1, -1),
+      testCase("Sprite read", // to reset round robin
+               idle, idle, idle,
+               idle, idle, read(1),
+               -1, 2),
+      testCase("CPU write conflict, other port feasible",
+               rwWrite(0), idle, idle,
+               read(0), read(1), idle,
+               0, 1),
+      testCase("CPU write conflict, conflict resolved",
+               idle, idle, idle,
+               read(0), idle, idle,
+               -1, 0)
 
 );