dave - Sentinel 65X

dave pushed to main at dave/gary

2024-09-09 00:15:11 +02:00

e5aabcbf4a vram/MemArbiter: remove unnecessary wires and fields

519eddc552 vram/MemArbiter: fix bug with write conflict avoidance

191cd1bfa2 vram: document MemArbiter, fix round-robin ordering bug

f31f64f5a2 vram: refactor MemArbiter into separate arbiters

2760bad965 vram: move VRAM to VRAMCore, in prep for arbitrated VRAM

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dave pushed to main at dave/gary

2024-09-08 04:50:06 +02:00

81e5264d22 vram: make arbiter clients and servers connectable

dave pushed to main at dave/gary

2024-09-08 01:58:53 +02:00

aa048537ef vram/MemArbiter: rewrite to use client/server idioms

dave pushed to main at dave/gary

2024-09-08 01:05:11 +02:00

b2b2c14009 vram/VRAM: finish the top-level VRAM module

dd551ce09b tasks.py: fix typo in synth process

fc4b212139 compile all tests before running them, so the outputs are grouped

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dave pushed to main at dave/gary

2024-09-07 21:11:49 +02:00

6e84e9c689 adjust 'inv genclk' to allow per-hardware PLLs

dave pushed to main at dave/gary

2024-09-07 19:33:09 +02:00

77b772c7ee tasks.py: improve handling of Bluespec libdirs

25d1806590 lib/ClockOut: hack module to export a clock as an ordinary signal

5e997201db hardware/sentinel65x: move top-level hw module to hw subdir

6fd040565c Grab the inout port fixer from bsc tree, wire it in

0005ad6fe5 sentinel65x/PLL: update PLL settings, fix generator

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dave pushed to main at dave/gary

2024-09-07 01:24:10 +02:00

f61328dac4 experiments/primitive_ram: clean up old testing code

930f9f7078 sentinel65x: start of Sentinel 65X top-level glue, with a PLL module

f7cb4b6ba2 vram/VRAM: early VRAM implementation

7560199251 tasks: support running nextpnr with a generic ulx3s pin map

2953106ec7 lib/ECP5_RAM: mark interfaces always_ready

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dave pushed to main at dave/gary

2024-09-06 09:13:57 +02:00

7f10694371 vram: get rid of old commented code

dave pushed to main at dave/gary

2024-09-06 09:08:32 +02:00

f010693b9b vram: compact the test output even more

dave pushed to main at dave/gary

2024-09-06 09:02:44 +02:00

71f422b8c1 vram: fix up documentation for MemoryArbiterWriter

dave pushed to main at dave/gary

2024-09-06 09:01:01 +02:00

e0d156cdd1 vram: a little more formatting of the vram test

dave pushed to main at dave/gary

2024-09-06 08:53:24 +02:00

d41ca7daae vram: tidy up formatting

dave pushed to main at dave/gary

2024-09-06 08:46:18 +02:00

60348fefd2 vram: one more arbiter test for port conflicts

dave pushed to main at dave/gary

2024-09-06 08:41:25 +02:00

5e22d03e15 vram: implement a MemoryArbiter for VRAM

2cd172cc73 tasks.py: add sim directory when running tests

efb5327f53 lib: clean up ECP5_RAM.v a bit

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dave pushed to main at dave/gary

2024-08-31 07:14:27 +02:00

119eeceaef Add some early testing harness for the sim DP16KD

a4a10becbf tasks.py: print one more intermediate output path

a0892fefcd sim/tb: add "bad" signals to make it easier to see wrong outputs

b913afd416 sim/tb: add wanted output signal, to help see incorrect outputs

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dave pushed to main at dave/gary

2024-08-31 03:55:46 +02:00

0b384c6619 sim: implementation of a simulation model DP16KD

dave pushed to main at dave/gary

2024-08-23 09:23:16 +02:00

e57f7e05b0 lib/ECP5_RAM: fixups based on checking synth output

febd840be0 Add svlint config

6666c1ca2d flake.nix: fix up xdot, add systemverilog linter

5d16ce23aa tasks.py: adjust yosys script

b73a211ec4 lib/ECP5_RAM: clean up old core, fix error in module docstring

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dave pushed to main at dave/gary

2024-08-20 18:16:11 +02:00

1ccd1b0072 lib/DelayLine: add a bit more documentation

2a8689564c tasks.py: remove debug message

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dave pushed to main at dave/gary

2024-08-20 09:55:29 +02:00

5df41d4b94 lib: use DelayLine in ECP5_RAM

dave pushed to main at dave/gary

2024-08-20 09:29:49 +02:00

f1e705fd31 lib: add more documentation

85e27554ec lib: add a DelayLine module

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