Commit Graph

99 Commits

Author SHA1 Message Date
David Anderson 9e53a6ba43 README.md: document current status, architecture image 2024-09-14 21:38:36 -07:00
David Anderson d3ab2fa433 debugger: start of a debugger client that uses the serial debug gateware 2024-09-14 20:32:40 -07:00
David Anderson 8a525d99a0 hardware/ulx3s: wire up blinky, tidy up the debugger a bit
IT WORKS!
2024-09-14 20:31:58 -07:00
David Anderson f7e3f36254 vram/VRAM: add tests for the arbitration glue and the entire VRAM stack 2024-09-14 20:26:55 -07:00
David Anderson 8247661a38 vram/VRAMCore: derive FShow for request and response types
Handy in unit tests to display the structs as they fly around.
2024-09-14 20:25:30 -07:00
David Anderson 65d13a0e50 vram/VRAM: only expect a response on reads
The VRAMCore doesn't generate responses for writes, so demanding one here
deadlocks the port the first time it writes something.
2024-09-14 20:24:40 -07:00
David Anderson e021e7d356 blinky/Blinky: a module that blinks a LED every second
Handy as a basic liveness test when you push stuff to an FPGA and
nothing happens.
2024-09-14 20:23:39 -07:00
David Anderson 227526c2b1 lib/ECP5_RAM: invert reset signal going into the primitive
Bluespec uses active-low reset signals, whereas the ECP5 primitives
use active-high. So this was holding the EBRs in reset after the rest
of the design was running. Oops.
2024-09-14 20:16:44 -07:00
David Anderson 8937e27d18 hardware/ulx3s: at last, a top-level design
This one targets a ULX3S dev board, since that's what I have. For now
it just wires up the debugger to VRAM and exposes it on the ulx3s serial
port.
2024-09-14 16:13:17 -07:00
David Anderson 2acf6aa661 tasks.py: support using nextpnr's "static" placer
It's still a WIP, but assuming its output is correct, it seems to net
a 5-10MHz boost to Fmax.
2024-09-14 16:12:28 -07:00
David Anderson 498aeae2f4 lib/PackUnpack: helper to pack and unpack values for transmission
With this you can feed a stream of bytes in and get multi-byte structs
out, or vice versa. Handy for hooking up stuff like debuggers to
narrower serial busses.
2024-09-14 13:01:07 -07:00
David Anderson 8ab867d2d2 lib/UART: move from debugger, it's generic enough 2024-09-13 23:05:48 -07:00
David Anderson b0126a7d16 flake.nix: grab the GUI version of nextpnr 2024-09-13 21:25:01 -07:00
David Anderson a08fd421fe experiments/uart: wire up a top-level UART for ulx3s 2024-09-13 21:24:29 -07:00
David Anderson 379ebf0411 debugger/UART: implement a UART with RTS/CTS flow control
In practice the flow control is unusable on ULX3S dev boards because
the CTS line isn't hooked up (it's instead wired to JTAG_TDO, to enable
the USB<>UART chip to serve a dual purpose as a bitbanged JTAG programmer)

Still, support for flow control is nice, for the future. And the UART
itself also works regardless of flow control, which is of course nice.
2024-09-13 21:24:29 -07:00
David Anderson cea5fde170 tasks.py: when running without a full pin map, synth for 100MHz
It doesn't matter hugely, but by default nextpnr synthesizes for 12MHz,
which doesn't force it to work too hard on the placement. By requesting
100MHz, it needs to try a bit harder on timing and gives results that
are a bit closer to the fully constrained outcomes.
2024-09-13 11:41:12 -07:00
David Anderson 1b85c3e216 lib/Strobe: rewrite, using better math and some sad type hacking
The numeric types vs numeric value thing sucks, but there's a mild
workaround where you just recurse through numeric types until you
find one that matches the value you wanted. It's icky, but it ensures
registers are exactly the correct width instead of relying on later
synthesis to find and execute the width reduction.
2024-09-13 11:41:12 -07:00
David Anderson b527a62ab8 lib/PinSync: switch back to Reg type, annotate required timing
I was mostly using a separate interface to be able to mark the methods
always_enabled and always_ready, but you can attach those annotations
to the module constructor instead.
2024-09-13 10:45:39 -07:00
David Anderson d10a548bc1 lib/GlitchFilter: a glitch filter to debounce input pins 2024-09-12 18:11:21 -07:00
David Anderson 07de394ddb lib/PinSync: use an explicit type
To make them more obviously not normal registers, and to add
annotations to make the scheduling more annoying if you try
holding them wrong.
2024-09-09 23:41:04 -07:00
David Anderson 2ff58b51d2 lib/PinSync: add a pin synchronizer for async inputs 2024-09-09 14:56:29 -07:00
David Anderson 4013be675e lib/Strobe: add a Strobe module to generate synchronization pulses 2024-09-09 13:10:50 -07:00
David Anderson b46d70fa07 vram/VRAMCore: cycle using prime numbers in tests
VRAMs are powers of two, so if memory wiring is wrong and we end up
with ram blocks mirrored at several points in the address space, we
want a write pattern that doesn't repeat cleanly on power of two
blocks. That way, a mirrored memory block cannot contain values that
are valid for all its locations.
2024-09-09 11:27:53 -07:00
David Anderson 719339e69f vram/MemArbiter: plumb verbose test flag into test 2024-09-09 11:22:07 -07:00
David Anderson 80391cefee lib/DelayLine: plumb verbose test flag into tests 2024-09-09 11:20:13 -07:00
David Anderson 1ca4ccff99 tasks.py: plumb -v to enable verbose test output 2024-09-09 11:17:08 -07:00
David Anderson 4b6b34e131 vram/VRAMCore: add tests, fix bug found by same 2024-09-09 11:16:21 -07:00
David Anderson ffb9f7c062 lib/Testing: add helper module to access test flags
Notably, this lets me plumb +v for verbose test output.
2024-09-09 11:15:51 -07:00
David Anderson 23a78eee9e vram/VRAM: a little more documentation tweaking 2024-09-08 23:44:45 -07:00
David Anderson 16af267ab6 vram/VRAM: tweak docs, remove unnecessary rule condition 2024-09-08 23:42:27 -07:00
David Anderson 1929bbe3cc vram/VRAM: at last, a video RAM, with all the gubbins 2024-09-08 23:39:12 -07:00
David Anderson fb57903021 vram/VRAMCore: make simulatable in Bluesim, tidy up 2024-09-08 23:19:39 -07:00
David Anderson 79b54ca86f vram/MemArbiter: add a granted_port method to make downstream wiring easier
To implement the mux tree that feeds into RAM ports, we need to know the
port index of the grantee to be able to wire it up. In theory we could
dispense with the per-port grant signal, but keeping it around allows
each client to deal with local concerns separate from the port routing.
2024-09-08 23:16:49 -07:00
David Anderson 2ebf399d62 vram/MemArbiter: remove MemArbiterClient, not needed right now 2024-09-08 22:44:39 -07:00
David Anderson eca95e0fb6 vram/VRAMCore: correct exports of the vram types 2024-09-08 15:37:47 -07:00
David Anderson 913c407224 hardware/sentinel65x: comment out logic
I'm not quite ready to define top-levels yet, and having this incomplete
code here makes 'inv build .' fail.
2024-09-08 15:16:34 -07:00
David Anderson e5aabcbf4a vram/MemArbiter: remove unnecessary wires and fields
While iterating many redundant bits were added. This removes them again,
keeping just (I think) the minimum necessary for the arbitrators to work.
2024-09-08 15:13:47 -07:00
David Anderson 519eddc552 vram/MemArbiter: fix bug with write conflict avoidance
Now that all arbiter ports can request to write, arbitration must check
both (write, read) and (read, write) conflicts, not just (write, read).
2024-09-08 15:02:55 -07:00
David Anderson 191cd1bfa2 vram: document MemArbiter, fix round-robin ordering bug 2024-09-08 14:10:52 -07:00
David Anderson f31f64f5a2 vram: refactor MemArbiter into separate arbiters
Rather than hardcode one architecture for GARY, the arbiters
are now split and can be allocated per-port. The arbiter interface
includes plumbing so that one arbiter can propagate a write conflict
to another, so it can still implement multi-port arbitration as long
as every client is statically allocated to one port.
2024-09-08 13:26:25 -07:00
David Anderson 2760bad965 vram: move VRAM to VRAMCore, in prep for arbitrated VRAM 2024-09-08 09:28:28 -07:00
David Anderson 69b7ce7f9e vram: adjust the MemoryArbiterClient interface a little 2024-09-08 09:27:25 -07:00
David Anderson 81e5264d22 vram: make arbiter clients and servers connectable 2024-09-07 19:49:43 -07:00
David Anderson aa048537ef vram/MemArbiter: rewrite to use client/server idioms
In preparation for making the two Connectable and defining an
arbitrated memory client/server for VRAM access.
2024-09-07 16:58:11 -07:00
David Anderson b2b2c14009 vram/VRAM: finish the top-level VRAM module
Well, for now at least. It can build 112KiB and 128KiB memories that
seem to synthesize to something reasonable.
2024-09-07 16:04:21 -07:00
David Anderson dd551ce09b tasks.py: fix typo in synth process 2024-09-07 16:03:52 -07:00
David Anderson fc4b212139 compile all tests before running them, so the outputs are grouped 2024-09-07 12:15:33 -07:00
David Anderson 6e84e9c689 adjust 'inv genclk' to allow per-hardware PLLs 2024-09-07 12:11:27 -07:00
David Anderson 77b772c7ee tasks.py: improve handling of Bluespec libdirs
To help divvy up the sources better, the build now makes a libpath
consisting of all directories that have bsv files in them, with a few
exceptions: hardware subdirs are target-specific so only get used if
they're the current build target. Experiments are random crap so get
the same treatment. And the 'sim' dir is only test helpers, so they
only get pulled in by tests.
2024-09-07 10:31:32 -07:00
David Anderson 25d1806590 lib/ClockOut: hack module to export a clock as an ordinary signal
Used to output a clock signal from an FPGA pin. The resultant output
signal is unclocked, so can be presented to any output at will.
2024-09-07 10:06:50 -07:00