hardware/ulx3s: at last, a top-level design
This one targets a ULX3S dev board, since that's what I have. For now it just wires up the debugger to VRAM and exposes it on the ulx3s serial port.
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package Top;
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import Connectable::*;
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import GetPut::*;
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import ClientServer::*;
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import PackUnpack::*;
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import UART::*;
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import VRAM::*;
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module mkUARTDebugger(Integer clock_frequency, Integer uart_bitrate, VRAMServer mem, UART_PHY ifc);
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UART _uart <- mkUART(clock_frequency, uart_bitrate);
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disableFlowControl(_uart); // Can't do hardware flow control on ULX3S
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Server#(Bit#(8), VRAMRequest) _decode <- mkUnpacker();
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Server#(VRAMResponse, Bit#(8)) _encode <- mkPacker();
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mkConnection(_uart.receive, _decode.request);
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mkConnection(_decode.response, mem.request);
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mkConnection(mem.response, _encode.request);
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mkConnection(_encode.response, _uart.send);
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return _uart.phy;
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endmodule
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interface Top;
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(* always_enabled,prefix="debug" *)
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method Action debugger_rx_in((* port="serial_in" *) bit b);
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(* always_ready,result="debug_serial_out" *)
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method bit debugger_tx_out();
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endinterface
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(* synthesize *)
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module mkTop(Top);
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////////////
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// Memory
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VRAM mem <- mkVRAM(128);
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////////////
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// Debug interface
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let debugger <- mkUARTDebugger(25_000_000, 115_200, mem.debugger);
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method debugger_rx_in = debugger.rx_in;
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method debugger_tx_out = debugger.tx_out;
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endmodule
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endpackage
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BLOCK RESETPATHS;
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BLOCK ASYNCPATHS;
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SYSCONFIG CONFIG_IOVOLTAGE=3.3 COMPRESS_CONFIG=ON MCCLK_FREQ=62 SLAVE_SPI_PORT=DISABLE MASTER_SPI_PORT=ENABLE SLAVE_PARALLEL_PORT=DISABLE;
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LOCATE COMP "CLK" SITE "G2";
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IOBUF PORT "CLK" PULLMODE=NONE IO_TYPE=LVCMOS33;
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FREQUENCY PORT "CLK" 25 MHZ;
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LOCATE COMP "RST_N" SITE "D6"; # BTN_PWRn (inverted logic)
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IOBUF PORT "RST_N" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
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LOCATE COMP "debug_serial_out" SITE "L4"; # FPGA transmits to ftdi
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LOCATE COMP "debug_serial_in" SITE "M1"; # FPGA receives from ftdi
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IOBUF PORT "debug_serial_out" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
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IOBUF PORT "debug_serial_in" PULLMODE=UP IO_TYPE=LVCMOS33;
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