hardware/ulx3s: at last, a top-level design

This one targets a ULX3S dev board, since that's what I have. For now
it just wires up the debugger to VRAM and exposes it on the ulx3s serial
port.
This commit is contained in:
David Anderson 2024-09-14 13:53:21 -07:00
parent 2acf6aa661
commit 8937e27d18
2 changed files with 63 additions and 0 deletions

47
hardware/ulx3s/Top.bsv Normal file
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package Top;
import Connectable::*;
import GetPut::*;
import ClientServer::*;
import PackUnpack::*;
import UART::*;
import VRAM::*;
module mkUARTDebugger(Integer clock_frequency, Integer uart_bitrate, VRAMServer mem, UART_PHY ifc);
UART _uart <- mkUART(clock_frequency, uart_bitrate);
disableFlowControl(_uart); // Can't do hardware flow control on ULX3S
Server#(Bit#(8), VRAMRequest) _decode <- mkUnpacker();
Server#(VRAMResponse, Bit#(8)) _encode <- mkPacker();
mkConnection(_uart.receive, _decode.request);
mkConnection(_decode.response, mem.request);
mkConnection(mem.response, _encode.request);
mkConnection(_encode.response, _uart.send);
return _uart.phy;
endmodule
interface Top;
(* always_enabled,prefix="debug" *)
method Action debugger_rx_in((* port="serial_in" *) bit b);
(* always_ready,result="debug_serial_out" *)
method bit debugger_tx_out();
endinterface
(* synthesize *)
module mkTop(Top);
////////////
// Memory
VRAM mem <- mkVRAM(128);
////////////
// Debug interface
let debugger <- mkUARTDebugger(25_000_000, 115_200, mem.debugger);
method debugger_rx_in = debugger.rx_in;
method debugger_tx_out = debugger.tx_out;
endmodule
endpackage

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BLOCK RESETPATHS;
BLOCK ASYNCPATHS;
SYSCONFIG CONFIG_IOVOLTAGE=3.3 COMPRESS_CONFIG=ON MCCLK_FREQ=62 SLAVE_SPI_PORT=DISABLE MASTER_SPI_PORT=ENABLE SLAVE_PARALLEL_PORT=DISABLE;
LOCATE COMP "CLK" SITE "G2";
IOBUF PORT "CLK" PULLMODE=NONE IO_TYPE=LVCMOS33;
FREQUENCY PORT "CLK" 25 MHZ;
LOCATE COMP "RST_N" SITE "D6"; # BTN_PWRn (inverted logic)
IOBUF PORT "RST_N" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
LOCATE COMP "debug_serial_out" SITE "L4"; # FPGA transmits to ftdi
LOCATE COMP "debug_serial_in" SITE "M1"; # FPGA receives from ftdi
IOBUF PORT "debug_serial_out" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
IOBUF PORT "debug_serial_in" PULLMODE=UP IO_TYPE=LVCMOS33;