experiments/uart: wire up a top-level UART for ulx3s
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package Top;
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import GetPut::*;
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import UART::*;
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(* always_enabled *)
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interface Top;
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(* prefix="" *)
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method Action rx_in((* port="rx_in" *) bit b);
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method bit tx_out();
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method Bit#(8) leds();
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endinterface
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(* synthesize *)
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module mkTop(Top);
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let _ret <- mkUART(100_000_000, 115_200);
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disableFlowControl(_ret);
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Reg#(Bit#(8)) leds_out <- mkReg(0);
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rule recv;
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let b <- _ret.receive.get();
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_ret.send.put(b);
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leds_out <= b;
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endrule
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method rx_in = _ret.phy.rx_in;
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method tx_out = _ret.phy.tx_out;
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method leds = leds_out._read;
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endmodule
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endpackage
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BLOCK RESETPATHS;
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BLOCK ASYNCPATHS;
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LOCATE COMP "CLK" SITE "G2";
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IOBUF PORT "CLK" PULLMODE=NONE IO_TYPE=LVCMOS33;
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FREQUENCY PORT "CLK" 150 MHZ;
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SYSCONFIG CONFIG_IOVOLTAGE=3.3 COMPRESS_CONFIG=ON MCCLK_FREQ=62 SLAVE_SPI_PORT=DISABLE MASTER_SPI_PORT=ENABLE SLAVE_PARALLEL_PORT=DISABLE;
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LOCATE COMP "tx_out" SITE "L4"; # FPGA transmits to ftdi
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LOCATE COMP "rx_in" SITE "M1"; # FPGA receives from ftdi
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IOBUF PORT "tx_out" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
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IOBUF PORT "rx_in" PULLMODE=UP IO_TYPE=LVCMOS33;
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LOCATE COMP "leds[7]" SITE "H3";
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LOCATE COMP "leds[6]" SITE "E1";
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LOCATE COMP "leds[5]" SITE "E2";
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LOCATE COMP "leds[4]" SITE "D1";
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LOCATE COMP "leds[3]" SITE "D2";
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LOCATE COMP "leds[2]" SITE "C1";
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LOCATE COMP "leds[1]" SITE "C2";
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LOCATE COMP "leds[0]" SITE "B2";
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IOBUF PORT "leds[0]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4;
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IOBUF PORT "leds[1]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4;
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IOBUF PORT "leds[2]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4;
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IOBUF PORT "leds[3]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4;
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IOBUF PORT "leds[4]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4;
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IOBUF PORT "leds[5]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4;
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IOBUF PORT "leds[6]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4;
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IOBUF PORT "leds[7]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4;
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LOCATE COMP "RST_N" SITE "B3";
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IOBUF PORT "RST_N" PULLMODE=DOWN IO_TYPE=LVCMOS33;
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