From a08fd421fecb977bad01c0dce9e1356151acbd18 Mon Sep 17 00:00:00 2001
From: David Anderson <dave@natulte.net>
Date: Mon, 9 Sep 2024 12:47:19 -0700
Subject: [PATCH] experiments/uart: wire up a top-level UART for ulx3s

---
 experiments/uart/Top.bsv     | 33 +++++++++++++++++++++++++++++++++
 experiments/uart/pin_map.lpf | 33 +++++++++++++++++++++++++++++++++
 2 files changed, 66 insertions(+)
 create mode 100644 experiments/uart/Top.bsv
 create mode 100644 experiments/uart/pin_map.lpf

diff --git a/experiments/uart/Top.bsv b/experiments/uart/Top.bsv
new file mode 100644
index 0000000..046c6f1
--- /dev/null
+++ b/experiments/uart/Top.bsv
@@ -0,0 +1,33 @@
+package Top;
+
+import GetPut::*;
+
+import UART::*;
+
+(* always_enabled *)
+interface Top;
+   (* prefix="" *)
+   method Action rx_in((* port="rx_in" *) bit b);
+   method bit tx_out();
+   method Bit#(8) leds();
+endinterface
+
+(* synthesize *)
+module mkTop(Top);
+   let _ret <- mkUART(100_000_000, 115_200);
+   disableFlowControl(_ret);
+
+   Reg#(Bit#(8)) leds_out <- mkReg(0);
+
+   rule recv;
+      let b <- _ret.receive.get();
+      _ret.send.put(b);
+      leds_out <= b;
+   endrule
+
+   method rx_in = _ret.phy.rx_in;
+   method tx_out = _ret.phy.tx_out;
+   method leds = leds_out._read;
+endmodule
+
+endpackage
diff --git a/experiments/uart/pin_map.lpf b/experiments/uart/pin_map.lpf
new file mode 100644
index 0000000..1933afe
--- /dev/null
+++ b/experiments/uart/pin_map.lpf
@@ -0,0 +1,33 @@
+BLOCK RESETPATHS;
+BLOCK ASYNCPATHS;
+
+LOCATE COMP "CLK" SITE "G2";
+IOBUF  PORT "CLK" PULLMODE=NONE IO_TYPE=LVCMOS33;
+FREQUENCY PORT "CLK" 150 MHZ;
+
+SYSCONFIG CONFIG_IOVOLTAGE=3.3 COMPRESS_CONFIG=ON MCCLK_FREQ=62 SLAVE_SPI_PORT=DISABLE MASTER_SPI_PORT=ENABLE SLAVE_PARALLEL_PORT=DISABLE;
+
+LOCATE COMP "tx_out" SITE "L4"; # FPGA transmits to ftdi
+LOCATE COMP "rx_in" SITE "M1"; # FPGA receives from ftdi
+IOBUF  PORT "tx_out" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
+IOBUF  PORT "rx_in" PULLMODE=UP IO_TYPE=LVCMOS33;
+
+LOCATE COMP "leds[7]" SITE "H3";
+LOCATE COMP "leds[6]" SITE "E1";
+LOCATE COMP "leds[5]" SITE "E2";
+LOCATE COMP "leds[4]" SITE "D1";
+LOCATE COMP "leds[3]" SITE "D2";
+LOCATE COMP "leds[2]" SITE "C1";
+LOCATE COMP "leds[1]" SITE "C2";
+LOCATE COMP "leds[0]" SITE "B2";
+IOBUF  PORT "leds[0]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4;
+IOBUF  PORT "leds[1]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4;
+IOBUF  PORT "leds[2]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4;
+IOBUF  PORT "leds[3]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4;
+IOBUF  PORT "leds[4]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4;
+IOBUF  PORT "leds[5]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4;
+IOBUF  PORT "leds[6]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4;
+IOBUF  PORT "leds[7]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4;
+
+LOCATE COMP "RST_N" SITE "B3";
+IOBUF  PORT "RST_N" PULLMODE=DOWN IO_TYPE=LVCMOS33;