Commit Graph

115 Commits

Author SHA1 Message Date
David Anderson 9ad69d3e3c debugger: crank the debug port up to 1.3Mbps
With this, full memory read-out takes ~1s.
2024-09-19 22:14:00 -07:00
David Anderson 5e66d8b205 debugger: load all 128k of VRAM 2024-09-19 21:10:48 -07:00
David Anderson 2156d824c5 hardware/ulx3s: integrate new debugger, bump VRAM back to 128Kb 2024-09-19 20:55:27 -07:00
David Anderson 0d4855fc21 debugger: implement burst reading 2024-09-19 20:50:42 -07:00
David Anderson 789d8d002b debugger/Debugger: return correct magic from ping commands 2024-09-19 20:39:58 -07:00
David Anderson ee1aecf0b9 debugger/Debugger: adjust urgency annotations, use full VRAM in tests 2024-09-19 17:36:10 -07:00
David Anderson 1acec6d835 vram/VRAMCore: fix timing bug with slow readers
The internal EBR array must stall new operations if there's a pending
read result that hasn't been retired yet. All that clever stuff with
non-blocking DelayLines and all that? Yeah, spoiler alert, there's a
reason guarded FIFOs are the preferred API for this stuff. Play unsafe
games, win unsafe prizes.
2024-09-19 14:37:05 -07:00
David Anderson af91f1bda8 debugger/Debugger: add an actual debug module
Introduces a new serial wire format, and a ReadRange command to
dump larger chunks of memory at once.
2024-09-18 21:23:22 -07:00
David Anderson 770f515a72 delete log.txt, mistakenly committed 2024-09-16 19:24:07 -07:00
David Anderson 700a301468 debugger: more UI tweaks and playing with layout 2024-09-16 19:23:37 -07:00
David Anderson 8c729698a8 debugger: implement scrolling in the hex view 2024-09-16 16:10:24 -07:00
David Anderson e2f4103fdc debugger: more hacking, hex editor with full editing now works 2024-09-16 15:53:55 -07:00
David Anderson 12ddbeb508 debugger: start of a debugging TUI for GARY
Uses the serial debug module and currently only works with
hardware/ulx3s, probably only on my specific machine where the
USB serial port is mapped _just so_. But it does work. Very WIP
unclean code, but checkpointing because it can hex view and hexedit
correctly.
2024-09-16 11:20:20 -07:00
David Anderson eb2bb40fd3 lib/ECP5_RAM: fix wiring of address bits
When using more than 1 bit data words, you have to use a subset of the
14 address bits that the primitive offers. I was feeding addresses into
the lower N bits of the primitive (e.g. lower 12 bits for a 4-bit memory),
but it turns out you're supposed to use the _upper_ N address bits.
2024-09-16 11:18:46 -07:00
David Anderson 76a1a36006 vram/VRAM: expand the full size test to check neighbor writes
As part of debugging why my writes seemed to get mirrored across a
stripe of 4 bytes. This test verifies that writing two contiguous
addresses reads back the correct value, when run against the simulated
ECP5 EBR model.
2024-09-16 11:17:42 -07:00
David Anderson f45ff0d105 flake.nix: update to Go 1.23 2024-09-16 11:17:14 -07:00
David Anderson 9e53a6ba43 README.md: document current status, architecture image 2024-09-14 21:38:36 -07:00
David Anderson d3ab2fa433 debugger: start of a debugger client that uses the serial debug gateware 2024-09-14 20:32:40 -07:00
David Anderson 8a525d99a0 hardware/ulx3s: wire up blinky, tidy up the debugger a bit
IT WORKS!
2024-09-14 20:31:58 -07:00
David Anderson f7e3f36254 vram/VRAM: add tests for the arbitration glue and the entire VRAM stack 2024-09-14 20:26:55 -07:00
David Anderson 8247661a38 vram/VRAMCore: derive FShow for request and response types
Handy in unit tests to display the structs as they fly around.
2024-09-14 20:25:30 -07:00
David Anderson 65d13a0e50 vram/VRAM: only expect a response on reads
The VRAMCore doesn't generate responses for writes, so demanding one here
deadlocks the port the first time it writes something.
2024-09-14 20:24:40 -07:00
David Anderson e021e7d356 blinky/Blinky: a module that blinks a LED every second
Handy as a basic liveness test when you push stuff to an FPGA and
nothing happens.
2024-09-14 20:23:39 -07:00
David Anderson 227526c2b1 lib/ECP5_RAM: invert reset signal going into the primitive
Bluespec uses active-low reset signals, whereas the ECP5 primitives
use active-high. So this was holding the EBRs in reset after the rest
of the design was running. Oops.
2024-09-14 20:16:44 -07:00
David Anderson 8937e27d18 hardware/ulx3s: at last, a top-level design
This one targets a ULX3S dev board, since that's what I have. For now
it just wires up the debugger to VRAM and exposes it on the ulx3s serial
port.
2024-09-14 16:13:17 -07:00
David Anderson 2acf6aa661 tasks.py: support using nextpnr's "static" placer
It's still a WIP, but assuming its output is correct, it seems to net
a 5-10MHz boost to Fmax.
2024-09-14 16:12:28 -07:00
David Anderson 498aeae2f4 lib/PackUnpack: helper to pack and unpack values for transmission
With this you can feed a stream of bytes in and get multi-byte structs
out, or vice versa. Handy for hooking up stuff like debuggers to
narrower serial busses.
2024-09-14 13:01:07 -07:00
David Anderson 8ab867d2d2 lib/UART: move from debugger, it's generic enough 2024-09-13 23:05:48 -07:00
David Anderson b0126a7d16 flake.nix: grab the GUI version of nextpnr 2024-09-13 21:25:01 -07:00
David Anderson a08fd421fe experiments/uart: wire up a top-level UART for ulx3s 2024-09-13 21:24:29 -07:00
David Anderson 379ebf0411 debugger/UART: implement a UART with RTS/CTS flow control
In practice the flow control is unusable on ULX3S dev boards because
the CTS line isn't hooked up (it's instead wired to JTAG_TDO, to enable
the USB<>UART chip to serve a dual purpose as a bitbanged JTAG programmer)

Still, support for flow control is nice, for the future. And the UART
itself also works regardless of flow control, which is of course nice.
2024-09-13 21:24:29 -07:00
David Anderson cea5fde170 tasks.py: when running without a full pin map, synth for 100MHz
It doesn't matter hugely, but by default nextpnr synthesizes for 12MHz,
which doesn't force it to work too hard on the placement. By requesting
100MHz, it needs to try a bit harder on timing and gives results that
are a bit closer to the fully constrained outcomes.
2024-09-13 11:41:12 -07:00
David Anderson 1b85c3e216 lib/Strobe: rewrite, using better math and some sad type hacking
The numeric types vs numeric value thing sucks, but there's a mild
workaround where you just recurse through numeric types until you
find one that matches the value you wanted. It's icky, but it ensures
registers are exactly the correct width instead of relying on later
synthesis to find and execute the width reduction.
2024-09-13 11:41:12 -07:00
David Anderson b527a62ab8 lib/PinSync: switch back to Reg type, annotate required timing
I was mostly using a separate interface to be able to mark the methods
always_enabled and always_ready, but you can attach those annotations
to the module constructor instead.
2024-09-13 10:45:39 -07:00
David Anderson d10a548bc1 lib/GlitchFilter: a glitch filter to debounce input pins 2024-09-12 18:11:21 -07:00
David Anderson 07de394ddb lib/PinSync: use an explicit type
To make them more obviously not normal registers, and to add
annotations to make the scheduling more annoying if you try
holding them wrong.
2024-09-09 23:41:04 -07:00
David Anderson 2ff58b51d2 lib/PinSync: add a pin synchronizer for async inputs 2024-09-09 14:56:29 -07:00
David Anderson 4013be675e lib/Strobe: add a Strobe module to generate synchronization pulses 2024-09-09 13:10:50 -07:00
David Anderson b46d70fa07 vram/VRAMCore: cycle using prime numbers in tests
VRAMs are powers of two, so if memory wiring is wrong and we end up
with ram blocks mirrored at several points in the address space, we
want a write pattern that doesn't repeat cleanly on power of two
blocks. That way, a mirrored memory block cannot contain values that
are valid for all its locations.
2024-09-09 11:27:53 -07:00
David Anderson 719339e69f vram/MemArbiter: plumb verbose test flag into test 2024-09-09 11:22:07 -07:00
David Anderson 80391cefee lib/DelayLine: plumb verbose test flag into tests 2024-09-09 11:20:13 -07:00
David Anderson 1ca4ccff99 tasks.py: plumb -v to enable verbose test output 2024-09-09 11:17:08 -07:00
David Anderson 4b6b34e131 vram/VRAMCore: add tests, fix bug found by same 2024-09-09 11:16:21 -07:00
David Anderson ffb9f7c062 lib/Testing: add helper module to access test flags
Notably, this lets me plumb +v for verbose test output.
2024-09-09 11:15:51 -07:00
David Anderson 23a78eee9e vram/VRAM: a little more documentation tweaking 2024-09-08 23:44:45 -07:00
David Anderson 16af267ab6 vram/VRAM: tweak docs, remove unnecessary rule condition 2024-09-08 23:42:27 -07:00
David Anderson 1929bbe3cc vram/VRAM: at last, a video RAM, with all the gubbins 2024-09-08 23:39:12 -07:00
David Anderson fb57903021 vram/VRAMCore: make simulatable in Bluesim, tidy up 2024-09-08 23:19:39 -07:00
David Anderson 79b54ca86f vram/MemArbiter: add a granted_port method to make downstream wiring easier
To implement the mux tree that feeds into RAM ports, we need to know the
port index of the grantee to be able to wire it up. In theory we could
dispense with the per-port grant signal, but keeping it around allows
each client to deal with local concerns separate from the port routing.
2024-09-08 23:16:49 -07:00
David Anderson 2ebf399d62 vram/MemArbiter: remove MemArbiterClient, not needed right now 2024-09-08 22:44:39 -07:00