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hardware/ulx3s: integrate new debugger, bump VRAM back to 128Kb

This commit is contained in:
David Anderson 2024-09-18 21:31:34 -07:00
parent 0d4855fc21
commit 2156d824c5
1 changed files with 11 additions and 7 deletions
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18
hardware/ulx3s/Top.bsv
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@ -8,18 +8,22 @@ import Blinky::*;
import PackUnpack::*;
import UART::*;
import VRAM::*;
import Debugger::*;
module mkUARTDebugger(Integer clock_frequency, Integer uart_bitrate, VRAMServer mem, UART_PHY ifc);
UART uart <- mkUART(clock_frequency, uart_bitrate);
disableFlowControl(uart); // Can't do hardware flow control on ULX3S
let uart_client = toGPClient(uart.receive, uart.send);
Server#(Bit#(8), VRAMRequest) decode <- mkUnpacker();
Server#(VRAMResponse, Bit#(8)) encode <- mkPacker();
Server#(Bit#(8), DebugRequest) decode <- mkUnpacker();
Server#(DebugResponse, Bit#(8)) encode <- mkPacker();
let bytes_server = toGPServer(decode.request, encode.response);
let debug_client = toGPClient(decode.response, encode.request);
mkConnection(uart_client, bytes_server);
mkConnection(uart.receive, decode.request);
mkConnection(decode.response, mem.request);
mkConnection(mem.response, encode.request);
mkConnection(encode.response, uart.send);
let debug <- mkDebugger();
mkConnection(debug_client, debug.server);
mkConnection(debug.vram, mem);
return uart.phy;
endmodule
@ -38,7 +42,7 @@ endinterface
module mkTop(Top);
////////////
// Memory
VRAM mem <- mkVRAM(4);
VRAM mem <- mkVRAM(128);
////////////
// Debugging