diff --git a/hardware/ulx3s/Top.bsv b/hardware/ulx3s/Top.bsv
index 06bc782..98675ac 100644
--- a/hardware/ulx3s/Top.bsv
+++ b/hardware/ulx3s/Top.bsv
@@ -8,18 +8,22 @@ import Blinky::*;
 import PackUnpack::*;
 import UART::*;
 import VRAM::*;
+import Debugger::*;
 
 module mkUARTDebugger(Integer clock_frequency, Integer uart_bitrate, VRAMServer mem, UART_PHY ifc);
    UART uart <- mkUART(clock_frequency, uart_bitrate);
    disableFlowControl(uart); // Can't do hardware flow control on ULX3S
+   let uart_client = toGPClient(uart.receive, uart.send);
 
-   Server#(Bit#(8), VRAMRequest) decode <- mkUnpacker();
-   Server#(VRAMResponse, Bit#(8)) encode <- mkPacker();
+   Server#(Bit#(8), DebugRequest) decode <- mkUnpacker();
+   Server#(DebugResponse, Bit#(8)) encode <- mkPacker();
+   let bytes_server = toGPServer(decode.request, encode.response);
+   let debug_client = toGPClient(decode.response, encode.request);
+   mkConnection(uart_client, bytes_server);
 
-   mkConnection(uart.receive, decode.request);
-   mkConnection(decode.response, mem.request);
-   mkConnection(mem.response, encode.request);
-   mkConnection(encode.response, uart.send);
+   let debug <- mkDebugger();
+   mkConnection(debug_client, debug.server);
+   mkConnection(debug.vram, mem);
 
    return uart.phy;
 endmodule
@@ -38,7 +42,7 @@ endinterface
 module mkTop(Top);
    ////////////
    // Memory
-   VRAM mem <- mkVRAM(4);
+   VRAM mem <- mkVRAM(128);
 
    ////////////
    // Debugging