debugger/Debugger: adjust urgency annotations, use full VRAM in tests
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@ -117,6 +117,7 @@ interface Debugger;
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endinterface
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// mkDebugger constructs a GARY debugger.
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(* descending_urgency="mem_response,issue_range,start_req" *)
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module mkDebugger(Debugger);
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FIFOF#(DebugRequest) req <- mkPipelineFIFOF();
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FIFOF#(DebugResponse) resp <- mkBypassFIFOF();
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@ -131,8 +132,6 @@ module mkDebugger(Debugger);
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return read_resp_cnt != 0;
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endfunction
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(* descending_urgency="mem_response,issue_range,start_req" *)
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rule start_req (req.notEmpty && !busy());
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case (req.first) matches
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tagged Ping: begin
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@ -173,6 +172,7 @@ module mkDebugger(Debugger);
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read_resp_cnt <= read_resp_cnt-1;
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endrule
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interface server = toGPServer(req, resp);
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interface vram = toGPClient(mem_req, mem_resp);
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endmodule
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@ -6,7 +6,7 @@ import Connectable::*;
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import StmtFSM::*;
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import Assert::*;
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import VRAMCore::*;
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import VRAM::*;
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import Debugger::*;
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import Testing::*;
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@ -14,9 +14,9 @@ module mkTB();
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let testflags <- mkTestFlags();
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let cycles <- mkCycleCounter();
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let vram <- mkVRAMCore(4);
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let vram <- mkVRAM(4);
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let dut <- mkDebugger();
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mkConnection(dut.vram, vram.portA);
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mkConnection(dut.vram, vram.debugger);
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function Action put(DebugRequest req);
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return action
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@ -53,6 +53,8 @@ module mkTB();
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put(tagged MemByteOp VRAMRequest { addr: 2, data: tagged Valid 66 });
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put(tagged MemByteOp VRAMRequest { addr: 3, data: tagged Valid 91 });
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put(tagged MemByteOp VRAMRequest { addr: 4, data: tagged Valid 154 });
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put(tagged MemByteOp VRAMRequest { addr: 5, data: tagged Valid 201 });
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put(tagged MemByteOp VRAMRequest { addr: 6, data: tagged Valid 243 });
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action
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put(tagged MemByteOp VRAMRequest { addr: 1, data: tagged Invalid });
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@ -77,7 +79,7 @@ module mkTB();
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endaction
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action
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put(tagged ReadRange ReadRange { start: 0, count: 5 });
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put(tagged ReadRange ReadRange { start: 0, count: 7 });
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cycles.reset();
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endaction
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@ -108,11 +110,21 @@ module mkTB();
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dynamicAssert(read == VRAMResponse{data: 154}, "wrong read response");
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dynamicAssert(cycles == 7, "wrong debugger delay");
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endaction
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action
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let read <- get();
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dynamicAssert(read == VRAMResponse{data: 201}, "wrong read response");
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dynamicAssert(cycles == 8, "wrong debugger delay");
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endaction
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action
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let read <- get();
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dynamicAssert(read == VRAMResponse{data: 243}, "wrong read response");
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dynamicAssert(cycles == 9, "wrong debugger delay");
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endaction
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// Result of the final byte read
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action
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let read <- get();
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dynamicAssert(read == VRAMResponse{data: 42}, "wrong read response");
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dynamicAssert(cycles == 10, "wrong debugger delay");
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dynamicAssert(cycles == 12, "wrong debugger delay");
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endaction
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endseq));
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endmodule
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