From ee1aecf0b9c8df2aded17a7c5d58067aae0875e6 Mon Sep 17 00:00:00 2001
From: David Anderson <dave@natulte.net>
Date: Wed, 18 Sep 2024 21:31:34 -0700
Subject: [PATCH] debugger/Debugger: adjust urgency annotations, use full VRAM
 in tests

---
 debugger/Debugger.bsv      |  4 ++--
 debugger/Debugger_Test.bsv | 22 +++++++++++++++++-----
 2 files changed, 19 insertions(+), 7 deletions(-)

diff --git a/debugger/Debugger.bsv b/debugger/Debugger.bsv
index 21b038d..3527c60 100644
--- a/debugger/Debugger.bsv
+++ b/debugger/Debugger.bsv
@@ -117,6 +117,7 @@ interface Debugger;
 endinterface
 
 // mkDebugger constructs a GARY debugger.
+(* descending_urgency="mem_response,issue_range,start_req" *)
 module mkDebugger(Debugger);
    FIFOF#(DebugRequest) req <- mkPipelineFIFOF();
    FIFOF#(DebugResponse) resp <- mkBypassFIFOF();
@@ -131,8 +132,6 @@ module mkDebugger(Debugger);
       return read_resp_cnt != 0;
    endfunction
 
-   (* descending_urgency="mem_response,issue_range,start_req" *)
-
    rule start_req (req.notEmpty && !busy());
       case (req.first) matches
          tagged Ping: begin
@@ -173,6 +172,7 @@ module mkDebugger(Debugger);
       read_resp_cnt <= read_resp_cnt-1;
    endrule
 
+
    interface server = toGPServer(req, resp);
    interface vram = toGPClient(mem_req, mem_resp);
 endmodule
diff --git a/debugger/Debugger_Test.bsv b/debugger/Debugger_Test.bsv
index 1e4e2f5..537c0fe 100644
--- a/debugger/Debugger_Test.bsv
+++ b/debugger/Debugger_Test.bsv
@@ -6,7 +6,7 @@ import Connectable::*;
 import StmtFSM::*;
 import Assert::*;
 
-import VRAMCore::*;
+import VRAM::*;
 import Debugger::*;
 import Testing::*;
 
@@ -14,9 +14,9 @@ module mkTB();
    let testflags <- mkTestFlags();
    let cycles <- mkCycleCounter();
 
-   let vram <- mkVRAMCore(4);
+   let vram <- mkVRAM(4);
    let dut <- mkDebugger();
-   mkConnection(dut.vram, vram.portA);
+   mkConnection(dut.vram, vram.debugger);
 
    function Action put(DebugRequest req);
       return action
@@ -53,6 +53,8 @@ module mkTB();
          put(tagged MemByteOp VRAMRequest { addr: 2, data: tagged Valid 66 });
          put(tagged MemByteOp VRAMRequest { addr: 3, data: tagged Valid 91 });
          put(tagged MemByteOp VRAMRequest { addr: 4, data: tagged Valid 154 });
+         put(tagged MemByteOp VRAMRequest { addr: 5, data: tagged Valid 201 });
+         put(tagged MemByteOp VRAMRequest { addr: 6, data: tagged Valid 243 });
 
          action
             put(tagged MemByteOp VRAMRequest { addr: 1, data: tagged Invalid });
@@ -77,7 +79,7 @@ module mkTB();
          endaction
 
          action
-            put(tagged ReadRange ReadRange { start: 0, count: 5 });
+            put(tagged ReadRange ReadRange { start: 0, count: 7 });
             cycles.reset();
          endaction
 
@@ -108,11 +110,21 @@ module mkTB();
              dynamicAssert(read == VRAMResponse{data: 154}, "wrong read response");
              dynamicAssert(cycles == 7, "wrong debugger delay");
          endaction
+         action
+             let read <- get();
+             dynamicAssert(read == VRAMResponse{data: 201}, "wrong read response");
+             dynamicAssert(cycles == 8, "wrong debugger delay");
+         endaction
+         action
+             let read <- get();
+             dynamicAssert(read == VRAMResponse{data: 243}, "wrong read response");
+             dynamicAssert(cycles == 9, "wrong debugger delay");
+         endaction
          // Result of the final byte read
          action
              let read <- get();
              dynamicAssert(read == VRAMResponse{data: 42}, "wrong read response");
-             dynamicAssert(cycles == 10, "wrong debugger delay");
+             dynamicAssert(cycles == 12, "wrong debugger delay");
          endaction
       endseq));
 endmodule