debugger/Debugger: add an actual debug module
Introduces a new serial wire format, and a ReadRange command to dump larger chunks of memory at once.
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package Debugger;
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import GetPut::*;
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import ClientServer::*;
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import FIFOF::*;
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import SpecialFIFOs::*;
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import VRAM::*;
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export ReadRange(..);
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export DebugRequest(..);
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export DebugResponse(..);
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export Debugger(..), mkDebugger;
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// ReadRange is a request to read a range of bytes.
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typedef struct {
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VRAMAddr start;
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UInt#(8) count;
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} ReadRange deriving (Eq, FShow);
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// DebugRequest is a request sent to the debugger.
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typedef union tagged {
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// Ping is a probe to check the connection to the debugger. The
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// debugger responds with 0xEA (Ω in code page 437) to identify
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// itself as a GARY debugger. The eschatological symbol for the end
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// of everything seems appropriate for the level of desperation
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// where you reach for the debug interface.
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//
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// Did you know Ω featured on the mission patch of STS-135, the
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// final flight of the US Space Shuttle program?
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//
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// "Having fired the imagination of a generation,
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// a ship like no other, its place in history secured,
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// the space shuttle pulls into port for the last time.
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// Its voyage, at an end."
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void Ping;
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// MemByteOp requests a read or write of a single byte of
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// memory. The associated VRAMRequest gets passed unmodified to the
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// memory port. For reads, produces a single VRAMResponse with the
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// data byte. For writes, no response.
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VRAMRequest MemByteOp;
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// ReadRange requests a read of a range of memory. It's equivalent
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// to N read MemByteOps, but the memory operations are pipelined,
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// enabling 3x faster readout.
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ReadRange ReadRange;
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} DebugRequest deriving (Eq, FShow);
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// DebugResponse is the debugger's response to a command. Depending on
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// the command, one DebugRequest may result in 0, 1 or many
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// DebugResponses. Requests are fully processed and responded to
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// before following requests are processed.
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typedef VRAMResponse DebugResponse;
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// DebugCmd is the value of the Cmd byte in raw encoded RawDebugReq.
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typedef enum {
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Ping = 'h7F, // To force the enum to be Bit#(7)
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ReadByte = 1,
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WriteByte = 2,
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ReadRange = 3
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} DebugCmd deriving (Bits, Eq, FShow);
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// RawDebugReq is the bit encoding of a DebugRequest. It is 32 bits
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// for all commands, in a format that's reasonably easy to assemble
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// from the client side.
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typedef struct {
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DebugCmd cmd;
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VRAMAddr addr;
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VRAMData data;
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} RawDebugReq deriving (Bits, Eq, FShow);
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instance Bits#(DebugRequest, 32);
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function Bit#(32) pack(DebugRequest r);
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case (r) matches
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tagged Ping:
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return pack(RawDebugReq{
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cmd: Ping,
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addr: 0,
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data: 0
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});
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tagged MemByteOp .req:
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if (req.data matches tagged Valid .data)
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return pack(RawDebugReq{
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cmd: WriteByte,
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addr: req.addr,
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data: data
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});
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else
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return pack(RawDebugReq{
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cmd: ReadByte,
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addr: req.addr,
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data: 0
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});
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tagged ReadRange .req:
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return pack(RawDebugReq{
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cmd: ReadRange,
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addr: req.start,
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data: unpack(pack(req.count))
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});
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endcase
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endfunction
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function DebugRequest unpack(Bit#(32) b);
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RawDebugReq raw = unpack(b);
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case (raw.cmd)
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Ping: return tagged Ping;
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ReadByte: return tagged MemByteOp VRAMRequest{addr: raw.addr, data: tagged Invalid};
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WriteByte: return tagged MemByteOp VRAMRequest{addr: raw.addr, data: tagged Valid raw.data};
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ReadRange: return tagged ReadRange ReadRange{start: raw.addr, count: unpack(pack(raw.data))};
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endcase
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endfunction
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endinstance
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// A Debugger provides debug access to GARY.
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interface Debugger;
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interface Server#(DebugRequest, DebugResponse) server;
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interface Client#(VRAMRequest, VRAMResponse) vram;
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endinterface
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// mkDebugger constructs a GARY debugger.
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module mkDebugger(Debugger);
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FIFOF#(DebugRequest) req <- mkPipelineFIFOF();
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FIFOF#(DebugResponse) resp <- mkBypassFIFOF();
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FIFOF#(VRAMRequest) mem_req <- mkBypassFIFOF();
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FIFOF#(VRAMResponse) mem_resp <- mkPipelineFIFOF();
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Reg#(VRAMAddr) next_read_addr <- mkReg(0);
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Reg#(UInt#(8)) read_issue_cnt <- mkReg(0);
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Reg#(UInt#(8)) read_resp_cnt <- mkReg(0);
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function Bool busy();
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return read_resp_cnt != 0;
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endfunction
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(* descending_urgency="mem_response,issue_range,start_req" *)
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rule start_req (req.notEmpty && !busy());
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case (req.first) matches
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tagged Ping: begin
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req.deq();
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resp.enq(DebugResponse{data: 0});
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end
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tagged MemByteOp .op: begin
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mem_req.enq(op);
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req.deq();
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if (op.data matches tagged Invalid)
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read_resp_cnt <= 1;
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end
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tagged ReadRange .range: begin
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mem_req.enq(VRAMRequest{
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addr: range.start,
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data: tagged Invalid
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});
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req.deq();
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next_read_addr <= range.start+1;
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read_issue_cnt <= range.count-1;
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read_resp_cnt <= range.count;
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end
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endcase
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endrule
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rule issue_range (read_issue_cnt > 0);
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mem_req.enq(VRAMRequest{
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addr: next_read_addr,
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data: tagged Invalid
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});
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next_read_addr <= next_read_addr+1;
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read_issue_cnt <= read_issue_cnt-1;
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endrule
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rule mem_response (mem_resp.notEmpty);
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resp.enq(mem_resp.first);
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mem_resp.deq();
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read_resp_cnt <= read_resp_cnt-1;
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endrule
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interface server = toGPServer(req, resp);
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interface vram = toGPClient(mem_req, mem_resp);
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endmodule
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endpackage
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@ -0,0 +1,120 @@
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package Debugger_Test;
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import GetPut::*;
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import ClientServer::*;
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import Connectable::*;
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import StmtFSM::*;
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import Assert::*;
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import VRAMCore::*;
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import Debugger::*;
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import Testing::*;
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module mkTB();
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let testflags <- mkTestFlags();
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let cycles <- mkCycleCounter();
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let vram <- mkVRAMCore(4);
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let dut <- mkDebugger();
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mkConnection(dut.vram, vram.portA);
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function Action put(DebugRequest req);
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return action
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if (testflags.verbose)
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$display("%0d (%0d): Debugger.put( ", cycles.all, cycles, fshow(req), ")");
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dut.server.request.put(req);
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endaction;
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endfunction
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function ActionValue#(DebugResponse) get();
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return actionvalue
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let ret <- dut.server.response.get();
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if (testflags.verbose)
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$display("%0d (%0d): Debugger.get() = ", cycles.all, cycles, fshow(ret));
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return ret;
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endactionvalue;
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endfunction
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runTest(200,
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mkTest("Debugger", seq
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action
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put(tagged Ping);
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cycles.reset();
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endaction
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action
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let pong <- get();
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dynamicAssert(pong == VRAMResponse{data: 0}, "wrong pong response");
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dynamicAssert(cycles == 1, "wrong debugger delay");
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endaction
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put(tagged MemByteOp VRAMRequest { addr: 0, data: tagged Valid 0 });
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put(tagged MemByteOp VRAMRequest { addr: 1, data: tagged Valid 42 });
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put(tagged MemByteOp VRAMRequest { addr: 2, data: tagged Valid 66 });
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put(tagged MemByteOp VRAMRequest { addr: 3, data: tagged Valid 91 });
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put(tagged MemByteOp VRAMRequest { addr: 4, data: tagged Valid 154 });
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action
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put(tagged MemByteOp VRAMRequest { addr: 1, data: tagged Invalid });
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cycles.reset();
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endaction
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action
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let read <- get();
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dynamicAssert(read == VRAMResponse{data: 42}, "wrong read response");
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dynamicAssert(cycles == 3, "wrong debugger delay");
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endaction
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action
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put(tagged MemByteOp VRAMRequest { addr: 2, data: tagged Invalid });
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cycles.reset();
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endaction
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action
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let read <- get();
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dynamicAssert(read == VRAMResponse{data: 66}, "wrong read response");
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dynamicAssert(cycles == 3, "wrong debugger delay");
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endaction
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action
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put(tagged ReadRange ReadRange { start: 0, count: 5 });
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cycles.reset();
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endaction
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put(tagged MemByteOp VRAMRequest { addr: 1, data: tagged Invalid });
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action
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let read <- get();
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dynamicAssert(read == VRAMResponse{data: 0}, "wrong read response");
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dynamicAssert(cycles == 3, "wrong debugger delay");
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endaction
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action
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let read <- get();
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dynamicAssert(read == VRAMResponse{data: 42}, "wrong read response");
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dynamicAssert(cycles == 4, "wrong debugger delay");
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endaction
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action
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let read <- get();
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dynamicAssert(read == VRAMResponse{data: 66}, "wrong read response");
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dynamicAssert(cycles == 5, "wrong debugger delay");
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endaction
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action
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let read <- get();
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dynamicAssert(read == VRAMResponse{data: 91}, "wrong read response");
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dynamicAssert(cycles == 6, "wrong debugger delay");
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endaction
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action
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let read <- get();
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dynamicAssert(read == VRAMResponse{data: 154}, "wrong read response");
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dynamicAssert(cycles == 7, "wrong debugger delay");
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endaction
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// Result of the final byte read
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action
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let read <- get();
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dynamicAssert(read == VRAMResponse{data: 42}, "wrong read response");
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dynamicAssert(cycles == 10, "wrong debugger delay");
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endaction
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endseq));
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endmodule
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endpackage
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