David Anderson
519eddc552
vram/MemArbiter: fix bug with write conflict avoidance
...
Now that all arbiter ports can request to write, arbitration must check
both (write, read) and (read, write) conflicts, not just (write, read).
2024-09-08 15:02:55 -07:00
David Anderson
2760bad965
vram: move VRAM to VRAMCore, in prep for arbitrated VRAM
2024-09-08 09:28:28 -07:00
David Anderson
aa048537ef
vram/MemArbiter: rewrite to use client/server idioms
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In preparation for making the two Connectable and defining an
arbitrated memory client/server for VRAM access.
2024-09-07 16:58:11 -07:00
David Anderson
b2b2c14009
vram/VRAM: finish the top-level VRAM module
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Well, for now at least. It can build 112KiB and 128KiB memories that
seem to synthesize to something reasonable.
2024-09-07 16:04:21 -07:00
David Anderson
f61328dac4
experiments/primitive_ram: clean up old testing code
2024-09-06 16:23:49 -07:00
David Anderson
f7cb4b6ba2
vram/VRAM: early VRAM implementation
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Only checked up to mkByteRAMArray, main VRAM still WIP
2024-09-06 16:11:55 -07:00
David Anderson
ab20db44f4
vram: rename MemoryArbiter to something shorter
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As I implement the whole transaction-level modeling thing with
arbitration, the interface names are getting longer and longer.
2024-09-06 10:04:20 -07:00
David Anderson
5e22d03e15
vram: implement a MemoryArbiter for VRAM
2024-09-05 23:39:21 -07:00
David Anderson
e57f7e05b0
lib/ECP5_RAM: fixups based on checking synth output
2024-08-23 00:22:48 -07:00
David Anderson
5df41d4b94
lib: use DelayLine in ECP5_RAM
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Cleans up the code nicely, and still produces the correct logic.
2024-08-20 00:54:50 -07:00
David Anderson
27da4958d2
experiments/rmw_ram: document failed/paused memory trickery experiments
2024-08-19 15:39:43 -07:00
David Anderson
da6ea4cf42
lib: flesh out the ECP5 EBR modules, write copious documentation
2024-08-18 16:12:57 -07:00
David Anderson
a69cc878ce
experiments/primitive_ram: customize the clock/reset of one of the RAM ports
2024-08-17 16:41:24 -07:00
David Anderson
8d2261e245
lib: initial implementation of an ECP5 EBR primitive
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Only the core unconditioned primitive right now, and still needs refining.
2024-08-17 15:43:36 -07:00
David Anderson
e6fa717507
Experiment comparing bsc-contrib's video timing generator with brute force
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Brute force is a naively written state machine that combines both horizontal
and vertical timings into one, in a way that unrolls comically badly. It's
obviously uncompetitive as-is, but I wanted to use that as a starting point
to see how much bsc and yosys would still be able to cope with it.
The result: the worse code takes much longer for bluespec to evaluate, and it
consumes ~4x the amount of logic elements after synthesis. Less terrible than
I expected, to be honest!
2024-08-15 00:22:51 -07:00
David Anderson