lib: flesh out the ECP5 EBR modules, write copious documentation
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@ -2,22 +2,25 @@ package Top;
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import ECP5_RAM::*;
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(* always_enabled *)
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//(* always_enabled *)
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interface Top;
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method Action put(UInt#(3) select, Bool write, Bit#(12) address, Bit#(4) data);
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method Bit#(4) read();
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interface EBRPort#(Bit#(12), Bit#(4)) ram1;
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//interface EBRPort#(Bit#(14), Bit#(1)) ram2;
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interface EBRPort#(void, void) ram2;
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endinterface
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(* synthesize *)
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module mkTop(Clock extClk, Reset extRst, Top ifc);
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ECP5_EBRPortConfig cfgA = defaultValue;
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cfgA.clk = tagged Valid extClk;
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cfgA.rstN = tagged Valid extRst;
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ECP5_EBRPortConfig cfgB = defaultValue;
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ECP5_EBRCore#(Bit#(12), Bit#(4), UInt#(12), UInt#(4)) ram <- mkECP5_EBRCore(cfgA, cfgB);
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module mkTop(Clock clk2, Reset rst2, Top ifc);
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EBRPortConfig cfgA = defaultValue;
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cfgA.write_mode = Normal;
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EBRPortConfig cfgB = defaultValue;
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cfgB.clk = tagged Valid clk2;
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cfgB.rstN = tagged Valid rst2;
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cfgB.register_output = True;
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let r <- mkEBR(cfgA, cfgB);
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method put = ram.portA.put;
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method read = ram.portA.read;
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interface EBRPort ram1 = r.portA;
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interface EBRPort ram2 = r.portB;
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endmodule
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endpackage
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702
lib/ECP5_RAM.bsv
702
lib/ECP5_RAM.bsv
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@ -1,204 +1,425 @@
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////////////////////////////////////////////////////////////
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package ECP5_RAM;
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import DReg::*;
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import Printf::*;
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import ToString::*;
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import StmtFSM::*;
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// ECP5_EBRWriteMode specifies what the EBR outputs on a write cycle.
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export EBRWriteMode(..);
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export EBRPortConfig(..);
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export EBRPort(..);
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export EBR(..);
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export mkEBRCore;
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export mkEBR;
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////////////////////////////////////////////////////////////
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// Configuration types
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//
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// The exported block RAMs in this package have one or more ports,
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// where each port is independently configurable. Not all parameters
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// are exposed, notably reset behavior is hardcoded to synchronous
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// reset and release. This is purely because I don't yet understand
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// Bluespec's reset semantics well enough to be confident in exposing
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// async reset without messing it up.
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//
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// The exported EBRPortConfig type is internally expanded into an
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// EBRPortConfig_Resolved. This expansion process resolves defaults,
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// (e.g. assigning a default clock if none was provided), derives some
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// additional values that implementations need (e.g. the widths of the
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// data and address I/Os as regular integers), and checks the
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// configuration for consistency errors (e.g. an address type larger
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// than what the hardware can support).
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// EBRWriteMode specifies an EBR port's output for a write operation,
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// if any.
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typedef enum {
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// In Normal mode, the EBR's output on a write cycle is undefined.
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// In Normal mode, write operations do not output a value.
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Normal,
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// In WriteThrough mode, the EBR outputs the new value at the
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// written address.
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// In WriteThrough mode, write operations output the value that was
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// written.
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WriteThrough,
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// In ReadBeforeWrite mode, the EBR outputs the prior value of the
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// written address. ReadBeforeWrite is only available on 9 and 18
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// bit ports.
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// In ReadBeforeWrite mode, write operations output the value that
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// was overwritten. This mode is only available on 9-bit and 18-bit
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// EBR configurations.
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ReadBeforeWrite
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} ECP5_EBRWriteMode deriving (Bits, Eq);
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} EBRWriteMode deriving (Bits, Eq);
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// ECP5_EBRPortConfig is the static configuration of an EBR port.
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// EBRPortConfig is the configuration of an EBR port.
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typedef struct {
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// clk, if specified, is the Clock to use for the port. If
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// unspecified, uses the module default clock.
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// unspecified, uses the module's default clock.
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Maybe#(Clock) clk;
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// rstN, if specified, is the Reset to use for the port. If
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// unspecified, uses the module default reset.
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// unspecified, uses the module's default reset.
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Maybe#(Reset) rstN;
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// By default, ECP5 EBRs only register the input address and write
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// data, giving a 1-cycle latency for operations. If
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// registered_output is true, the output value is also registered,
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// resulting in 2 cycles of latency but shorter datapaths.
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Bool registered_output;
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// chip_select_addr is the chip address of this EBR port. put
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// method invocations whose select argument don't match this
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// address are ignored.
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// Whether to register the output of the EBR port.
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//
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// EBR ports always register their inputs, to present predictable
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// signals to the memory circuitry. Ports can optionally also
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// enable an output register, which adds latency to operations but
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// decouples the memory's internal latency from the logic connected
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// to the output. This may allow designs to run at higher clock
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// speeds, outweighing the added cycle overhead.
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//
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// With non-registered output, EBR operations have a latency of 1
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// cycle. Registering the output increases that to 2 cycles. By
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// default, the output is not registered.
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Bool register_output;
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// chip_select_addr is the port's chip select address. The port
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// ignores put operations that don't provide a matching chip_select
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// argument.
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//
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// This is intended to make it easier to construct larger memories
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// out of multiple EBR ports: by configuring different chip
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// addresses for each port, the inputs to the overall memory can be
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// routed directly to all EBR ports, rather than having to provide
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// your own address decoding and routing logic.
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UInt#(3) chip_select_addr;
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// write_mode specifies the output's behavior for write operations.
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ECP5_EBRWriteMode write_mode;
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} ECP5_EBRPortConfig;
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// write_mode specifies what the EBR port outputs for write
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// operations. In the default Normal mode, write operations do not
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// produce any output.
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EBRWriteMode write_mode;
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} EBRPortConfig deriving (Eq);
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instance DefaultValue#(ECP5_EBRPortConfig);
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defaultValue = ECP5_EBRPortConfig{
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instance DefaultValue#(EBRPortConfig);
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defaultValue = EBRPortConfig{
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clk: defaultValue,
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rstN: defaultValue,
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registered_output: False,
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register_output: False,
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chip_select_addr: 0,
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write_mode: Normal
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};
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endinstance
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(* always_ready *)
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interface ECP5_EBRCoreInnerPort;
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// Put starts a read or write operation, if select's value matches
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// the port's configured chip_select_addr.
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method Action put(UInt#(3) select, Bool write, Bit#(14) address, Bit#(18) data);
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// Read returns the value on the EBR's output port. The output
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// value is only defined when the read follows a put with the
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// correct number of latency cycles for the port's configuration.
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method Bit#(18) read();
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endinterface
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// EBRPortConfig_Resolved is an elaborated version of EBRPortConfig,
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// with all defaults and overrides resolved to their concrete values,
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// port widths made explicit and verified.
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typedef struct {
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// These fields are the same as in EBRPortConfig. If the port is
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// not in use, they are tied to default values that avoid any logic
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// or wires being generated outside of the EBR.
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Clock clk;
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Reset rstN;
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Bool register_output;
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UInt#(3) chip_select_addr;
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EBRWriteMode write_mode;
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interface ECP5_EBRCoreInner;
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interface ECP5_EBRCoreInnerPort portA;
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interface ECP5_EBRCoreInnerPort portB;
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endinterface
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// These are values derived by resolvePortCfg from an EBRPortConfig
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// and other contextual information from a module
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// instantiation. These are values that modules need to derive, so
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// we derive them all once here instead of forcing each module to
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// do so.
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// mkECP5_EBRCoreInner instantiates an ECP5 EBR primitive with the
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// given configuration. The returned interface has full-width I/O
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// ports
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import "BVI" ECP5_RAM =
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module mkECP5_EBRCoreInner#(ECP5_EBRPortConfig port_a,
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ECP5_EBRPortConfig port_b,
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Integer portA_width,
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Integer portB_width)
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(ECP5_EBRCoreInner);
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// enabled is whether the port is in use at all. Modules omit all
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// glue logic and wiring for disabled ports, resulting in zero
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// burden during synthesis (other than consuming an EBR primitive,
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// but presumably you're using the other port still).
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//
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// Enabled is true if the memory's type for values is a non-zero
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// number of bits. In particular, eanbled=False if the caller uses
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// 'void' as the port's data type.
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Bool enabled;
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// addr_width is the bit width of addresses. resolvePortCfg ensures
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// that it is less than or equal to the maximum address width that
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// makes sense for data_width.
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Integer addr_width;
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// data_width is the bit width of input and output values. It is
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// always one of the valid values for the EBR primitive: 1, 2, 4, 9
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// or 18.
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Integer data_width;
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// write_outputs_data is whether write_mode is one of the modes
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// where write operations output a value. Modules use this to
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// generate the appropriate conditions for port reads.
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Bool write_outputs_data;
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// operation_latency is how many cycles elapse between put()
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// executing to read() being ready. It is used to generate the
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// appropriate conditions for port reads.
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//
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// Operation latency on enabled ports is 2 if the output is
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// registered, or 1 for unregistered output. Disabled ports have 0
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// latency, meaning no timing logic is needed.
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Integer operation_latency;
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// chip_select_addr_str is the string encoding of chip_select_addr
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// that the EBR hardware primitive wants for its configuration
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// parameter.
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String chip_select_addr_str;
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// write_mode_str is the string encoding of write_mode that hte EBR
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// hardware primitive wants for its configuration parameter.
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String write_mode_str;
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// register_output_str is the string encoding of register_output
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// that the EBR hardware primitive wants for its configuration
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// parameter.
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String register_output_str;
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} EBRPortConfig_Resolved;
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let defClk <- exposeCurrentClock;
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let defRstN <- exposeCurrentReset;
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let portA_bsv_clock = case (port_a.clk) matches
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tagged Invalid: defClk;
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tagged Valid .clk: clk;
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endcase;
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let portA_bsv_rstN = case (port_a.rstN) matches
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tagged Invalid: defRstN;
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tagged Valid .rstN: rstN;
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endcase;
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let portB_bsv_clock = case (port_b.clk) matches
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tagged Invalid: defClk;
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tagged Valid .clk: clk;
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endcase;
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let portB_bsv_rstN = case (port_b.rstN) matches
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tagged Invalid: defRstN;
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tagged Valid .rstN: rstN;
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endcase;
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default_clock no_clock;
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default_reset no_reset;
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input_clock portA_clk(CLKA, (* unused *)CLKA_GATE) = portA_bsv_clock;
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input_reset portA_rstN(RSTA) clocked_by(portA_clk) = portA_bsv_rstN;
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input_clock portB_clk(CLKB, (* unused *)CLKB_GATE) = portB_bsv_clock;
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input_reset portB_rstN(RSTB) clocked_by(portB_clk) = portB_bsv_rstN;
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parameter DATA_WIDTH_A = portA_width;
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parameter REGMODE_A = port_a.registered_output ? "OUTREG" : "NOREG";
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parameter CSDECODE_A = "0b000"; //$format("0b%b", port_a.chip_select_addr);
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parameter WRITEMODE_A = case (port_a.write_mode) matches
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Normal: "NORMAL";
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WriteThrough: "WRITETHROUGH";
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ReadBeforeWrite: "READBEFOREWRITE";
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endcase;
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parameter DATA_WIDTH_B = portB_width;
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parameter REGMODE_B = port_b.registered_output ? "OUTREG" : "NOREG";
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parameter CSDECODE_B = "0b000"; //$format("0b%b", port_b.chip_select_addr);
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parameter WRITEMODE_B = case (port_b.write_mode) matches
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Normal: "NORMAL";
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WriteThrough: "WRITETHROUGH";
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ReadBeforeWrite: "READBEFOREWRITE";
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endcase;
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port OCEA = True;
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port OCEB = True;
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interface ECP5_EBRCoreInnerPort portA;
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method put((*reg*)CSA, (*reg*)WEA, (*reg*)ADA, (*reg*)DIA) enable(CEA) clocked_by(portA_clk) reset_by(portA_rstN);
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method DOA read() clocked_by(portA_clk) reset_by(portA_rstN);
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endinterface
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interface ECP5_EBRCoreInnerPort portB;
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method put((*reg*)CSB, (*reg*)WEB, (*reg*)ADB, (*reg*)DIB) enable(CEB) clocked_by(portB_clk) reset_by(portB_rstN);
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method DOB read() clocked_by(portB_clk) reset_by(portB_rstN);
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endinterface
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schedule (portA.read) CF (portA.read, portA.put);
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schedule (portA.put) C (portA.put);
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schedule (portB.read) CF (portB.read, portB.put);
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schedule (portB.put) C (portB.put);
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endmodule : mkECP5_EBRCoreInner
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module checkSizes#(addr a, data d, String module_name, String port_name)(Empty)
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function EBRPortConfig_Resolved resolvePortCfg(String module_name, String port_name, addr a, data d, EBRPortConfig cfg, Clock defaultClk, Reset defaultRstN)
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provisos (Bits#(addr, addr_sz),
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Bits#(data, data_sz));
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let data_sz = valueOf(data_sz);
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let addr_sz = valueOf(addr_sz);
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let data_sz = valueOf(data_sz);
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let addr_max = case (data_sz) matches
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0: 0;
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1: 14;
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2: 13;
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4: 12;
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9: 11;
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18: 10;
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default: error(sprintf("invalid data width %d for port, must be one of 1,2,4,9,18", data_sz));
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default: error(sprintf("invalid data width %d for %s port %s, must be one of 0,1,2,4,9,18", data_sz, module_name, port_name));
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endcase;
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let enabled = data_sz != 0;
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let ret = ?;
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if (enabled)
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ret = EBRPortConfig_Resolved{
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enabled: True,
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clk: cfg.clk matches tagged Valid .clk ? clk : defaultClk,
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rstN: cfg.rstN matches tagged Valid .rstN ? rstN : defaultRstN,
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addr_width: addr_sz,
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data_width: data_sz,
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register_output: cfg.register_output,
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chip_select_addr: cfg.chip_select_addr,
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write_mode: cfg.write_mode,
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write_outputs_data: cfg.write_mode != Normal,
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operation_latency: cfg.register_output ? 2 : 1,
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chip_select_addr_str: sprintf("0b%03b", cfg.chip_select_addr),
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write_mode_str: case (cfg.write_mode) matches
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Normal: "NORMAL";
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WriteThrough: "WRITETHROUGH";
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ReadBeforeWrite: "READBEFOREWRITE";
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endcase,
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register_output_str: cfg.register_output ? "OUTREG": "NOREG"
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};
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else
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ret = EBRPortConfig_Resolved{
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enabled: False,
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clk: noClock,
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rstN: noReset,
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addr_width: 14,
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data_width: 18,
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register_output: False,
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chip_select_addr: 0,
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write_mode: Normal,
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write_outputs_data: False,
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operation_latency: 0,
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chip_select_addr_str: "0b000",
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write_mode_str: "NORMAL",
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register_output_str: "NOREG"
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};
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if (addr_sz > addr_max) begin
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addr dummy = ?;
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errorM(sprintf("The address type for port %s of %s is wider than the hardware can implement. "+
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"Address type %s has %d bits, maximum is %d",
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port_name, module_name,
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printType(typeOf(dummy)),
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addr_sz,
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addr_max));
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ret = error(sprintf("The address type for port %s of %s is wider than the hardware can implement. "+
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"Address type %s has %d bits, maximum is %d",
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port_name, module_name,
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printType(typeOf(dummy)),
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addr_sz,
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addr_max));
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end
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endmodule
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return ret;
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endfunction
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// ECP5_EBRCorePort is the raw interface to one port of an ECP5 EBR
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// memory block.
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////////////////////////////////////////////////////////////
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// Exported interfaces
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//
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// The port has no implicit conditions, it is the caller's
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// responsibility to wait the correct number of cycles after a put()
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// before capturing data with read(). The caller must wait 1 cycle for
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// unregistered ports, and 2 cycles for registered ports. When invoked
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// at other times, read() returns an unspecified arbitrary value.
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interface ECP5_EBRCorePort#(type addr, type data);
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// EBRPort is a port of an EBR memory.
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interface EBRPort#(type addr, type data);
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method Action put(UInt#(3) chip_select, Bool write, addr address, data datain);
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method data read();
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endinterface
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// ECP5_EBRCore is the raw interface to an ECP5 EBR memory block.
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//
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// The ports have no implicit conditions, the caller must wait the
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// correct number of latency cycles to get valid data.
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//
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// It is the caller's responsibility to enforce synchronization
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// between the ports, as specified in Lattice Technical Note 02204:
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// the two ports must not issue concurrent writes to the same address,
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// or a write concurrent with a read of the same address. If the two
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// ports are being operated from different clock domains, the caller
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// must implement appropriate synchronization to ensure that no
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// read-during-write or write-during-write races occur.
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interface ECP5_EBRCore#(type portA_addr, type portA_data, type portB_addr, type portB_data);
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interface ECP5_EBRCorePort#(portA_addr, portA_data) portA;
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interface ECP5_EBRCorePort#(portB_addr, portB_data) portB;
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// EBR is an EBR memory.
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interface EBR#(type portA_addr, type portA_data, type portB_addr, type portB_data);
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interface EBRPort#(portA_addr, portA_data) portA;
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interface EBRPort#(portB_addr, portB_data) portB;
|
||||
endinterface
|
||||
|
||||
// mkECP5_EBRCore instantiates an ECP5 EBR memory primitive with the
|
||||
// given configuration. This memory has no implicit or explicit
|
||||
// conditions, the caller is responsible for upholding the primitive's
|
||||
// timing and synchronization requirements.
|
||||
module mkECP5_EBRCore#(ECP5_EBRPortConfig port_a,
|
||||
ECP5_EBRPortConfig port_b)
|
||||
(ECP5_EBRCore#(addr_a, data_a, addr_b, data_b))
|
||||
////////////////////////////////////////////////////////////
|
||||
// Verilog import
|
||||
//
|
||||
// The raw primitive for EBR is called DP16KD. However, Lattice and
|
||||
// Yosys both expose it with the I/O ports exploded out into
|
||||
// individual bit signals, which is pretty horrible to plumb up here.
|
||||
//
|
||||
// Instead, ECP5_RAM.v defines a tiny Verilog wrapper, whose only
|
||||
// purpose is to group those individual bit signals back into
|
||||
// multi-bit ports that Bluespec can manipulate more elegantly.
|
||||
//
|
||||
// This wrapper exposes all the I/O ports with their maximum bit
|
||||
// width, even though there is no configuration that can use all the
|
||||
// bits. For example if you use all 14 address bits, you're only using
|
||||
// 1 data bit (16384x1b configuration). If you're using all 18 bits of
|
||||
// data, you're only using 10 address bits (1024x18b
|
||||
// configuration). We do this because we want to drive unused signals
|
||||
// to defined values, so we have to be able to see all of them.
|
||||
//
|
||||
// The exported wrapper modules defined further down translate these
|
||||
// large raw ports into proper Bluespec types, and handle the
|
||||
// necessary padding and truncation.
|
||||
|
||||
(* always_ready *)
|
||||
interface V_EBRPort;
|
||||
// Put starts an operation, if select's value matches the port's
|
||||
// configured chip_select_addr.
|
||||
method Action put(UInt#(3) select, Bool write, Bit#(14) address, Bit#(18) data);
|
||||
// Read provides the EBR's output value. At this raw layer, read
|
||||
// always returns a value, but that value is undefined unless a put
|
||||
// which generates output happened N cycles prior, where N is the
|
||||
// port's configured latency (see EBRPortConfig).
|
||||
//
|
||||
// It is the caller's responsibility to time reads correctly
|
||||
// relative to puts.
|
||||
method Bit#(18) read();
|
||||
endinterface
|
||||
|
||||
interface V_EBR;
|
||||
interface V_EBRPort portA;
|
||||
interface V_EBRPort portB;
|
||||
endinterface
|
||||
|
||||
// vEBRCoreInner instantiates a raw EBR primitive with the given
|
||||
// configuration.
|
||||
//
|
||||
// The returned interface has maximally wide types on all I/O, and
|
||||
// uses plain bit arrays. It also has no conditions on any methods,
|
||||
// it's the caller's reponsibility to time method calls appropriately.
|
||||
//
|
||||
// Nothing should use this module directly, except for mkEBRCore
|
||||
// below. mkEBRCore wraps the Verilog primitive in stronger types and
|
||||
// handles configuration edge cases (detecting invalid configs, tying
|
||||
// off unused ports), but otherwise presents the same "raw" primitive
|
||||
// from a semantic perspective. Anything you can build using
|
||||
// vMkEBRCore, you can build better with mkEBRCore.
|
||||
import "BVI" ECP5_RAM =
|
||||
module vMkEBRCore#(EBRPortConfig_Resolved cfgA,
|
||||
EBRPortConfig_Resolved cfgB)
|
||||
(V_EBR);
|
||||
|
||||
// EBRs are dual-port with independent clocks and resets on each
|
||||
// port, so we need to be careful to map things correctly. Unset
|
||||
// the default clock and reset entirely, so that the compiler
|
||||
// complains loudly if we forget to explicitly specify the
|
||||
// clocking/reset on a signal.
|
||||
default_clock no_clock;
|
||||
default_reset no_reset;
|
||||
|
||||
input_clock portA_clk(CLKA, (* unused *)CLKA_GATE) = cfgA.clk;
|
||||
input_reset portA_rstN(RSTA) clocked_by(portA_clk) = cfgA.rstN;
|
||||
|
||||
input_clock portB_clk(CLKB, (* unused *)CLKB_GATE) = cfgB.clk;
|
||||
input_reset portB_rstN(RSTB) clocked_by(portB_clk) = cfgB.rstN;
|
||||
|
||||
parameter DATA_WIDTH_A = cfgA.data_width;
|
||||
parameter REGMODE_A = cfgA.register_output ? "OUTREG" : "NOREG";
|
||||
parameter CSDECODE_A = cfgA.chip_select_addr_str;
|
||||
parameter WRITEMODE_A = cfgA.write_mode_str;
|
||||
|
||||
parameter DATA_WIDTH_B = cfgB.data_width;
|
||||
parameter REGMODE_B = cfgB.register_output ? "OUTREG" : "NOREG";
|
||||
parameter CSDECODE_B = cfgB.chip_select_addr_str;
|
||||
parameter WRITEMODE_B = cfgB.write_mode_str;
|
||||
|
||||
// The outputs of EBR ports also have an enable signal. It's
|
||||
// unclear why you'd want to suppress the output of things you
|
||||
// asked the memory to give you. Since I can't think of any use
|
||||
// for them, leave them always enabled if the corresponding port
|
||||
// is active.
|
||||
port OCEA = cfgA.enabled;
|
||||
port OCEB = cfgB.enabled;
|
||||
|
||||
interface V_EBRPort portA;
|
||||
method put((*reg*)CSA, (*reg*)WEA, (*reg*)ADA, (*reg*)DIA) enable(CEA) clocked_by(portA_clk) reset_by(portA_rstN);
|
||||
method DOA read() clocked_by(portA_clk) reset_by(portA_rstN);
|
||||
endinterface
|
||||
interface V_EBRPort portB;
|
||||
method put((*reg*)CSB, (*reg*)WEB, (*reg*)ADB, (*reg*)DIB) enable(CEB) clocked_by(portB_clk) reset_by(portB_rstN);
|
||||
method DOB read() clocked_by(portB_clk) reset_by(portB_rstN);
|
||||
endinterface
|
||||
|
||||
// A quick crash course on Bluespec's scheduling instructions.
|
||||
//
|
||||
// Bluespec's fundamental property is that rule execution is
|
||||
// serializable: all designs behave as if they execute a single
|
||||
// rule at a time, in some order. In the actual hardware
|
||||
// typically many rules execute in parallel on every cycle, but
|
||||
// that's just an optimization: the observed behavior of the
|
||||
// system must always be explainable by executing rules one at a
|
||||
// time, where each rule sees the effects of all previously
|
||||
// executed rules.
|
||||
//
|
||||
// When pulling Verilog modules into a Bluespec universe, the
|
||||
// compiler must be told explicitly what orders of execution are
|
||||
// valid, given the hardware's behavior. The canonical example
|
||||
// is a read of a register's value and a write to the same
|
||||
// register. Those two actions produce different system states
|
||||
// depending on which one executes first: if read-before-write,
|
||||
// the read sees the register's old value. In write-before-read,
|
||||
// the read sees the updated value.
|
||||
//
|
||||
// That's why, if you go digging into the low level Bluespec
|
||||
// definition of what a register is, you'll find a scheduling
|
||||
// annotation which says that if a read and a write both want to
|
||||
// happen (both methods are "enabled" in a clock cycle), the
|
||||
// read must execute before the write. When translated into
|
||||
// hardware, this matches familiar synchronous logic: on a given
|
||||
// cycle, your logic sees the previous cycle's value, and all
|
||||
// writes to registers happen at the "end" of the cycle.
|
||||
//
|
||||
// And so we come to the scheduling rules. Our annotations tell
|
||||
// the compiler how the memory's methods can be called, if
|
||||
// several of them are able to execute. Each scheduling
|
||||
// annotation is written as:
|
||||
//
|
||||
// schedule <method(s) A> ORDERING <method(s) B>
|
||||
//
|
||||
// This means: assuming that method(s) A and method(s) B both
|
||||
// want both execute, can both be executed without issues? And
|
||||
// if yes, do they need to execute in a specific order?
|
||||
//
|
||||
// The orderings you can specify are:
|
||||
//
|
||||
// - C : "conflict". The scheduler must pick a single one of A
|
||||
// or B to execute.
|
||||
// - CF : "conflict-free". A and B can both execute, and the
|
||||
// outcome is the same regardless of which executes first.
|
||||
// - SB : "schedule before". A and B can both execute, but A
|
||||
// must execute first to get correct results.
|
||||
// - SBR: "schedule before (restricted)". Same as SB, but A
|
||||
// and B must also execute from different rules.
|
||||
//
|
||||
// With that, here are the scheduling annotations for
|
||||
// vMkEBRCore.
|
||||
|
||||
// TODO: why is portA.read CF portA.put? Shouldn't that be SB to
|
||||
// match register semantics?
|
||||
schedule (portA.read) CF (portA.read);
|
||||
schedule (portA.read) SB (portA.put);
|
||||
schedule (portA.put) C (portA.put);
|
||||
schedule (portB.read) CF (portB.read);
|
||||
schedule (portB.read) SB (portB.put);
|
||||
schedule (portB.put) C (portB.put);
|
||||
endmodule : vMkEBRCore
|
||||
|
||||
////////////////////////////////////////////////////////////
|
||||
// Exported modules
|
||||
|
||||
// mkEBRCore instantiates one EBR memory block with the given
|
||||
// configuration.
|
||||
//
|
||||
// The returned ports have no implicit conditions. The caller is
|
||||
// responsible for upholding the block's timing and synchronization
|
||||
// requirements, following Lattice TN 02204.
|
||||
//
|
||||
// read() yields valid data 1 cycle after put() for ports configured
|
||||
// with unregistered output, or 2 cycles for registered outputs. At
|
||||
// all other times, the returned value is undefined.
|
||||
//
|
||||
// portA and portB must not concurrently write the same bits, or read
|
||||
// bits while the other is writing them. The stored value in a
|
||||
// write-write race is undefined, as is the read value in a write-read
|
||||
// race.
|
||||
module mkEBRCore#(EBRPortConfig cfgA,
|
||||
EBRPortConfig cfgB)
|
||||
(EBR#(addr_a, data_a, addr_b, data_b))
|
||||
provisos (Bits#(addr_a, addr_sz_a),
|
||||
Bits#(data_a, data_sz_a),
|
||||
Bits#(addr_b, addr_sz_b),
|
||||
|
|
@ -208,64 +429,171 @@ module mkECP5_EBRCore#(ECP5_EBRPortConfig port_a,
|
|||
Add#(addr_b_pad, addr_sz_b, 14),
|
||||
Add#(data_b_pad, data_sz_b, 18));
|
||||
|
||||
checkSizes(addr_a ' (?), data_a ' (?), "mkECP5_EBRCore", "A");
|
||||
checkSizes(addr_b ' (?), data_b ' (?), "mkECP5_EBRCore", "B");
|
||||
let defaultClk <- exposeCurrentClock;
|
||||
let defaultRstN <- exposeCurrentReset;
|
||||
let rcfgA = resolvePortCfg("mkEBRCore", "A", addr_a ' (?), data_a ' (?), cfgA, defaultClk, defaultRstN);
|
||||
let rcfgB = resolvePortCfg("mkEBRCore", "B", addr_b ' (?), data_b ' (?), cfgB, defaultClk, defaultRstN);
|
||||
|
||||
let inner <- mkECP5_EBRCoreInner(port_a, port_b, valueOf(data_sz_a), valueOf(data_sz_b));
|
||||
let vEBR <- vMkEBRCore(rcfgA, rcfgB);
|
||||
|
||||
interface ECP5_EBRCorePort portA;
|
||||
interface EBRPort portA;
|
||||
method Action put(UInt#(3) chip_select, Bool write, addr_a address, data_a datain);
|
||||
inner.portA.put(chip_select, write, zeroExtend(pack(address)), zeroExtend(pack(datain)));
|
||||
if (!rcfgA.enabled)
|
||||
noAction;
|
||||
else
|
||||
vEBR.portA.put(chip_select, write, zeroExtend(pack(address)), zeroExtend(pack(datain)));
|
||||
endmethod
|
||||
method data_a read();
|
||||
return unpack(truncate(inner.portA.read()));
|
||||
if (!rcfgA.enabled)
|
||||
return ?;
|
||||
else
|
||||
return unpack(truncate(vEBR.portA.read()));
|
||||
endmethod
|
||||
endinterface
|
||||
|
||||
interface ECP5_EBRCorePort portB;
|
||||
interface EBRPort portB;
|
||||
method Action put(UInt#(3) chip_select, Bool write, addr_b address, data_b datain);
|
||||
inner.portB.put(chip_select, write, zeroExtend(pack(address)), zeroExtend(pack(datain)));
|
||||
if (!rcfgB.enabled)
|
||||
noAction;
|
||||
else
|
||||
vEBR.portB.put(chip_select, write, zeroExtend(pack(address)), zeroExtend(pack(datain)));
|
||||
endmethod
|
||||
method data_b read();
|
||||
return unpack(truncate(inner.portB.read()));
|
||||
if (!rcfgB.enabled)
|
||||
return ?;
|
||||
else
|
||||
return unpack(truncate(vEBR.portB.read()));
|
||||
endmethod
|
||||
endinterface
|
||||
endmodule
|
||||
|
||||
module mkECP5_EBRCoreByte#(ECP5_EBRPortConfig port_a,
|
||||
ECP5_EBRPortConfig port_b)
|
||||
(ECP5_EBRCore#(addr_a, data_a, addr_b, data_b))
|
||||
provisos (Bits#(addr_a, 12),
|
||||
Bits#(data_a, 8),
|
||||
Bits#(addr_b, 12),
|
||||
Bits#(data_b, 8));
|
||||
// mkEBRCore instantiates one EBR memory block with the given
|
||||
// configuration.
|
||||
//
|
||||
// This module includes flow control for reads, but unlike the
|
||||
// standard library BRAM servers there is no flow control on puts. Put
|
||||
// is always_ready, and read behaves like a Wire: the result of each
|
||||
// put is available for a single cycle, and is lost if not read at
|
||||
// that time.
|
||||
module mkEBR#(EBRPortConfig cfgA,
|
||||
EBRPortConfig cfgB)
|
||||
(EBR#(addr_a, data_a, addr_b, data_b))
|
||||
provisos (Bits#(addr_a, addr_sz_a),
|
||||
Bits#(data_a, data_sz_a),
|
||||
Bits#(addr_b, addr_sz_b),
|
||||
Bits#(data_b, data_sz_b),
|
||||
Add#(addr_a_pad, addr_sz_a, 14),
|
||||
Add#(data_a_pad, data_sz_a, 18),
|
||||
Add#(addr_b_pad, addr_sz_b, 14),
|
||||
Add#(data_b_pad, data_sz_b, 18));
|
||||
|
||||
let ebr1 <- mkECP5_EBRCore(port_a, port_b);
|
||||
let ebr2 <- mkECP5_EBRCore(port_a, port_b);
|
||||
let defaultClk <- exposeCurrentClock;
|
||||
let defaultRstN <- exposeCurrentReset;
|
||||
let rcfgA = resolvePortCfg("mkEBR", "A", addr_a ' (?), data_a ' (?), cfgA, defaultClk, defaultRstN);
|
||||
let rcfgB = resolvePortCfg("mkEBR", "B", addr_b ' (?), data_b ' (?), cfgB, defaultClk, defaultRstN);
|
||||
|
||||
interface ECP5_EBRCorePort portA;
|
||||
let mem <- mkEBRCore(cfgA, cfgB);
|
||||
|
||||
WriteOnly#(Bool) portA_start_op = ?;
|
||||
ReadOnly#(Bool) portA_op_complete = ?;
|
||||
WriteOnly#(Bool) portB_start_op = ?;
|
||||
ReadOnly#(Bool) portB_op_complete = ?;
|
||||
|
||||
// TODO: this variable-depth register chain should be pulled into a
|
||||
// separate "delay line" module.
|
||||
if (!rcfgA.enabled) begin
|
||||
portA_start_op = discardingWriteOnly;
|
||||
portA_op_complete = constToReadOnly(False);
|
||||
end
|
||||
else if (rcfgA.register_output) begin
|
||||
let syncA1 <- mkDReg(False, clocked_by(rcfgA.clk), reset_by(rcfgA.rstN));
|
||||
let syncA2 <- mkReg(False, clocked_by(rcfgA.clk), reset_by(rcfgA.rstN));
|
||||
portA_start_op = regToWriteOnly(syncA1);
|
||||
portA_op_complete = regToReadOnly(syncA2);
|
||||
|
||||
(* no_implicit_conditions, fire_when_enabled *)
|
||||
rule syncA1_to_syncA2;
|
||||
syncA2 <= syncA1;
|
||||
endrule
|
||||
end
|
||||
else begin
|
||||
let syncA <- mkDReg(False, clocked_by(rcfgA.clk), reset_by(rcfgA.rstN));
|
||||
portA_start_op = regToWriteOnly(syncA);
|
||||
portA_op_complete = regToReadOnly(syncA);
|
||||
end
|
||||
|
||||
if (!rcfgB.enabled) begin
|
||||
portB_start_op = discardingWriteOnly;
|
||||
portB_op_complete = constToReadOnly(False);
|
||||
end
|
||||
else if (rcfgB.register_output) begin
|
||||
let syncB1 <- mkDReg(False, clocked_by(rcfgB.clk), reset_by(rcfgB.rstN));
|
||||
let syncB2 <- mkReg(False, clocked_by(rcfgB.clk), reset_by(rcfgB.rstN));
|
||||
portB_start_op = regToWriteOnly(syncB1);
|
||||
portB_op_complete = regToReadOnly(syncB2);
|
||||
|
||||
(* no_implicit_conditions, fire_when_enabled *)
|
||||
rule syncB1_to_syncB2;
|
||||
syncB2 <= syncB1;
|
||||
endrule
|
||||
end
|
||||
else begin
|
||||
let syncB1 <- mkDReg(False, clocked_by(rcfgB.clk), reset_by(rcfgB.rstN));
|
||||
portB_start_op = regToWriteOnly(syncB1);
|
||||
portB_op_complete = regToReadOnly(syncB1);
|
||||
end
|
||||
|
||||
interface EBRPort portA;
|
||||
method Action put(UInt#(3) chip_select, Bool write, addr_a address, data_a datain);
|
||||
let data_bits = pack(datain);
|
||||
ebr1.portA.put(chip_select, write, address, data_bits[7:4]);
|
||||
ebr2.portA.put(chip_select, write, address, data_bits[3:0]);
|
||||
mem.portA.put(chip_select, write, address, datain);
|
||||
if (rcfgA.write_outputs_data || !write)
|
||||
portA_start_op <= True;
|
||||
endmethod
|
||||
|
||||
method data_a read();
|
||||
return unpack({ebr1.portA.read(), ebr2.portA.read});
|
||||
method data_a read() if (rcfgA.enabled && portA_op_complete == True);
|
||||
return mem.portA.read();
|
||||
endmethod
|
||||
endinterface
|
||||
|
||||
interface ECP5_EBRCorePort portB;
|
||||
interface EBRPort portB;
|
||||
method Action put(UInt#(3) chip_select, Bool write, addr_b address, data_b datain);
|
||||
let data_bits = pack(datain);
|
||||
ebr1.portB.put(chip_select, write, address, data_bits[7:4]);
|
||||
ebr2.portB.put(chip_select, write, address, data_bits[3:0]);
|
||||
mem.portB.put(chip_select, write, address, datain);
|
||||
if (rcfgB.write_outputs_data || !write)
|
||||
portB_start_op <= True;
|
||||
endmethod
|
||||
|
||||
method data_b read();
|
||||
return unpack({ebr1.portB.read(), ebr2.portB.read});
|
||||
method data_b read() if (rcfgB.enabled && portB_op_complete == True);
|
||||
return mem.portB.read();
|
||||
endmethod
|
||||
endinterface
|
||||
endmodule
|
||||
endmodule : mkEBR
|
||||
|
||||
////////////////////////////////////////////////////////////
|
||||
// Utilities
|
||||
//
|
||||
// These are little helpers that I expected to find in the stdlib, but
|
||||
// aren't there. Thankfully, they are easy to write by following the
|
||||
// examples of similar helpers.
|
||||
|
||||
function WriteOnly#(a) discardingWriteOnly();
|
||||
return (interface WriteOnly
|
||||
method Action _write(a x);
|
||||
noAction;
|
||||
endmethod
|
||||
endinterface);
|
||||
endfunction
|
||||
|
||||
function WriteOnly#(a) regToWriteOnly(Reg#(a) r);
|
||||
return (interface WriteOnly
|
||||
method _write = r._write;
|
||||
endinterface);
|
||||
endfunction
|
||||
|
||||
function ReadOnly#(a) constToReadOnly(a x);
|
||||
return (interface ReadOnly
|
||||
method _read;
|
||||
return x;
|
||||
endmethod
|
||||
endinterface);
|
||||
endfunction
|
||||
|
||||
endpackage
|
||||
|
||||
|
|
|
|||
Loading…
Reference in New Issue