99 lines
2.8 KiB
Plaintext
99 lines
2.8 KiB
Plaintext
package DelayLine_Test;
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import Assert::*;
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import StmtFSM::*;
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import Testing::*;
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import Printf::*;
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import List::*;
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import DelayLine::*;
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module mkTB();
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let cycles <- mkTestCycleLimiter(100);
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function Stmt testDelayLine(DelayLine#(Int#(8)) delay, Bit#(32) wantDelay);
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seq
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$display(" RUN delay=%0d", wantDelay);
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action
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delay <= 42;
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cycles.reset_count();
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$display(" write cycle: %0d", cycles.cycles);
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endaction
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repeat (wantDelay-1)
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action
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if (delay.ready) begin
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$display("delay line ready after %0d cycles, want %0d", cycles.count, wantDelay);
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$finish;
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end
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endaction
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// Check the value coming off the delay line and the timing
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// separately, since the delay line read can be blocked by
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// implicit conditions.
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par
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dynamicAssert(delay == 42, "delay output was wrong value");
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action
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dynamicAssert(delay.ready == True, "delay line not ready when expected");
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if (cycles.count != wantDelay) begin
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$display("delay line ready after %0d cycles, want %0d", cycles.count, wantDelay);
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$finish;
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end
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$display(" ready cycle: %0d", cycles.cycles);
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endaction
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endpar
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dynamicAssert(delay.ready == False, "delay line still ready after value yield");
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$display(" OK delay=%0d", wantDelay);
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endseq;
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endfunction
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let delay0 <- mkDelayLine(0);
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let test0 = seq
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$display(" RUN delay=0");
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dynamicAssert(delay0.ready == False, "delay line ready before put");
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par
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action
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delay0 <= 42;
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$display(" write cycle: %0d", cycles.cycles);
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endaction
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action
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dynamicAssert(delay0.ready == True, "delay line not ready on same cycle");
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$display(" read cycle: %0d", cycles.cycles);
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endaction
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dynamicAssert(delay0 == 42, "delay line has wrong value");
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endpar
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dynamicAssert(delay0.ready == False, "delay line ready without write");
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$display(" OK delay=0");
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endseq;
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let delay1 <- mkDelayLine(1);
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let test1 = testDelayLine(delay1, 1);
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let delay2 <- mkDelayLine(2);
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let test2 = testDelayLine(delay2, 2);
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let delay3 <- mkDelayLine(3);
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let test3 = testDelayLine(delay3, 3);
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let delay4 <- mkDelayLine(4);
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let test4 = testDelayLine(delay4, 4);
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mkTest("DelayLine", seq
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test0;
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test1;
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test2;
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test3;
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test4;
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endseq);
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endmodule
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endpackage
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