David Anderson
85e27554ec
A delay line takes a write and echoes it back N cycles later, with N fixed at compile time. It's a handy primitive to have when wrapping Verilog blackbox modules because the blackbox often specifies something like having 2 cycles of latency, and so you need to bubble the fact that a write occurred 2 cycles ago through to the output so that you can wire up the right implicit conditions. |
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| lib | ||
| .gitignore | ||
| LICENSE | ||
| Requirements.md | ||
| flake.lock | ||
| flake.nix | ||
| tasks.py | ||