gary/lib
David Anderson 85e27554ec lib: add a DelayLine module
A delay line takes a write and echoes it back N cycles later,
with N fixed at compile time. It's a handy primitive to have
when wrapping Verilog blackbox modules because the blackbox
often specifies something like having 2 cycles of latency,
and so you need to bubble the fact that a write occurred 2
cycles ago through to the output so that you can wire up the
right implicit conditions.
2024-08-19 23:00:15 -07:00
..
DelayLine.bsv lib: add a DelayLine module 2024-08-19 23:00:15 -07:00
DelayLine_Test.bsv lib: add a DelayLine module 2024-08-19 23:00:15 -07:00
ECP5_RAM.bsv lib: flesh out the ECP5 EBR modules, write copious documentation 2024-08-18 16:12:57 -07:00
ECP5_RAM.v lib: fix port B reset wiring for ECP5_RAM 2024-08-17 16:38:52 -07:00
Testing.bsv lib: add a DelayLine module 2024-08-19 23:00:15 -07:00