package DelayLine_Test;

import Assert::*;
import StmtFSM::*;
import Testing::*;
import Printf::*;
import List::*;

import DelayLine::*;

module mkTB();
   let cycles <- mkTestCycleLimiter(100);

   function Stmt testDelayLine(DelayLine#(Int#(8)) delay, Bit#(32) wantDelay);
      seq
         $display("  RUN delay=%0d", wantDelay);

         action
            delay <= 42;
            cycles.reset_count();
            $display("    write cycle: %0d", cycles.cycles);
         endaction

         repeat (wantDelay-1)
         action
            if (delay.ready) begin
               $display("delay line ready after %0d cycles, want %0d", cycles.count, wantDelay);
               $finish;
            end
         endaction

         // Check the value coming off the delay line and the timing
         // separately, since the delay line read can be blocked by
         // implicit conditions.
         par
            dynamicAssert(delay == 42, "delay output was wrong value");

            action
               dynamicAssert(delay.ready == True, "delay line not ready when expected");
               if (cycles.count != wantDelay) begin
                  $display("delay line ready after %0d cycles, want %0d", cycles.count, wantDelay);
                  $finish;
               end
               $display("    ready cycle: %0d", cycles.cycles);
            endaction
         endpar

         dynamicAssert(delay.ready == False, "delay line still ready after value yield");

         $display("  OK  delay=%0d", wantDelay);
      endseq;
   endfunction

   let delay0 <- mkDelayLine(0);
   let test0 = seq
                  $display("  RUN delay=0");

                  dynamicAssert(delay0.ready == False, "delay line ready before put");

                  par
                     action
                        delay0 <= 42;
                        $display("    write cycle: %0d", cycles.cycles);
                     endaction
                     action
                        dynamicAssert(delay0.ready == True, "delay line not ready on same cycle");
                        $display("    read cycle: %0d", cycles.cycles);
                     endaction
                     dynamicAssert(delay0 == 42, "delay line has wrong value");
                  endpar

                  dynamicAssert(delay0.ready == False, "delay line ready without write");

                  $display("  OK  delay=0");
               endseq;

   let delay1 <- mkDelayLine(1);
   let test1 = testDelayLine(delay1, 1);

   let delay2 <- mkDelayLine(2);
   let test2 = testDelayLine(delay2, 2);

   let delay3 <- mkDelayLine(3);
   let test3 = testDelayLine(delay3, 3);

   let delay4 <- mkDelayLine(4);
   let test4 = testDelayLine(delay4, 4);

   mkTest("DelayLine", seq
      test0;
      test1;
      test2;
      test3;
      test4;
   endseq);
endmodule

endpackage