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Graphics Adapter for Retropixel Yeeting. An experiment for now, who knows what might happen.
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Bluespec 67%
Verilog 19.9%
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Python 4.3%
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David Anderson 77b772c7ee tasks.py: improve handling of Bluespec libdirs 
To help divvy up the sources better, the build now makes a libpath
consisting of all directories that have bsv files in them, with a few
exceptions: hardware subdirs are target-specific so only get used if
they're the current build target. Experiments are random crap so get
the same treatment. And the 'sim' dir is only test helpers, so they
only get pulled in by tests.
 		2024-09-07 10:31:32 -07:00
experiments experiments/primitive_ram: clean up old testing code 2024-09-06 16:23:49 -07:00
hardware/sentinel65x hardware/sentinel65x: move top-level hw module to hw subdir 2024-09-07 10:04:36 -07:00
images Add tentative requirements document to capture requests. 2024-08-14 09:39:42 -07:00
lib lib/ClockOut: hack module to export a clock as an ordinary signal 2024-09-07 10:06:50 -07:00
scripts Grab the inout port fixer from bsc tree, wire it in 2024-09-06 21:26:39 -07:00
sim Add some early testing harness for the sim DP16KD 2024-08-30 22:14:10 -07:00
vram vram/VRAM: early VRAM implementation 2024-09-06 16:11:55 -07:00
.gitignore add a simple build/test script 2024-08-14 09:39:42 -07:00
.svlint.toml Add svlint config 2024-08-23 00:21:15 -07:00
LICENSE Initial basic files 2024-08-13 22:24:20 -07:00
Requirements.md Requirements.md: fix image insertion syntax 2024-08-14 09:44:14 -07:00
flake.lock flake.lock: update tools 2024-09-06 21:17:32 -07:00
flake.nix sim: implementation of a simulation model DP16KD 2024-08-30 18:54:54 -07:00
tasks.py tasks.py: improve handling of Bluespec libdirs 2024-09-07 10:31:32 -07:00