David Anderson
7f10694371
vram: get rid of old commented code
2024-09-06 00:13:42 -07:00
David Anderson
f010693b9b
vram: compact the test output even more
2024-09-06 00:08:14 -07:00
David Anderson
71f422b8c1
vram: fix up documentation for MemoryArbiterWriter
2024-09-06 00:02:23 -07:00
David Anderson
e0d156cdd1
vram: a little more formatting of the vram test
...
Make it a bit more compact, for large test runs
2024-09-06 00:00:25 -07:00
David Anderson
d41ca7daae
vram: tidy up formatting
2024-09-05 23:51:21 -07:00
David Anderson
60348fefd2
vram: one more arbiter test for port conflicts
2024-09-05 23:46:01 -07:00
David Anderson
5e22d03e15
vram: implement a MemoryArbiter for VRAM
2024-09-05 23:39:21 -07:00
David Anderson
2cd172cc73
tasks.py: add sim directory when running tests
...
So that bluesim can find the DP16KD simulation model.
2024-08-31 00:00:59 -07:00
David Anderson
efb5327f53
lib: clean up ECP5_RAM.v a bit
2024-08-31 00:00:41 -07:00
David Anderson
119eeceaef
Add some early testing harness for the sim DP16KD
2024-08-30 22:14:10 -07:00
David Anderson
a4a10becbf
tasks.py: print one more intermediate output path
2024-08-30 20:06:36 -07:00
David Anderson
a0892fefcd
sim/tb: add "bad" signals to make it easier to see wrong outputs
2024-08-30 20:00:11 -07:00
David Anderson
b913afd416
sim/tb: add wanted output signal, to help see incorrect outputs
2024-08-30 19:56:08 -07:00
David Anderson
0b384c6619
sim: implementation of a simulation model DP16KD
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Not fully verified with tests yet, WIP
2024-08-30 18:54:54 -07:00
David Anderson
e57f7e05b0
lib/ECP5_RAM: fixups based on checking synth output
2024-08-23 00:22:48 -07:00
David Anderson
febd840be0
Add svlint config
2024-08-23 00:21:15 -07:00
David Anderson
6666c1ca2d
flake.nix: fix up xdot, add systemverilog linter
2024-08-23 00:20:45 -07:00
David Anderson
5d16ce23aa
tasks.py: adjust yosys script
2024-08-23 00:20:31 -07:00
David Anderson
b73a211ec4
lib/ECP5_RAM: clean up old core, fix error in module docstring
2024-08-20 19:25:04 -07:00
David Anderson
1ccd1b0072
lib/DelayLine: add a bit more documentation
2024-08-20 09:15:52 -07:00
David Anderson
2a8689564c
tasks.py: remove debug message
2024-08-20 09:13:36 -07:00
David Anderson
5df41d4b94
lib: use DelayLine in ECP5_RAM
...
Cleans up the code nicely, and still produces the correct logic.
2024-08-20 00:54:50 -07:00
David Anderson
f1e705fd31
lib: add more documentation
2024-08-20 00:29:32 -07:00
David Anderson
85e27554ec
lib: add a DelayLine module
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A delay line takes a write and echoes it back N cycles later,
with N fixed at compile time. It's a handy primitive to have
when wrapping Verilog blackbox modules because the blackbox
often specifies something like having 2 cycles of latency,
and so you need to bubble the fact that a write occurred 2
cycles ago through to the output so that you can wire up the
right implicit conditions.
2024-08-19 23:00:15 -07:00
David Anderson
27da4958d2
experiments/rmw_ram: document failed/paused memory trickery experiments
2024-08-19 15:39:43 -07:00
David Anderson
da6ea4cf42
lib: flesh out the ECP5 EBR modules, write copious documentation
2024-08-18 16:12:57 -07:00
David Anderson
a69cc878ce
experiments/primitive_ram: customize the clock/reset of one of the RAM ports
2024-08-17 16:41:24 -07:00
David Anderson
a23661a449
lib: default clocks and resets to the ambient ones from context
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Callers can still specify whacky cross-domain RAMs in the cfg, but the
default is what you usually want: a dual-port RAM with both ports in the
caller's clock/reset domain.
2024-08-17 16:39:45 -07:00
David Anderson
e64b990f80
lib: fix port B reset wiring for ECP5_RAM
2024-08-17 16:38:52 -07:00
David Anderson
8d2261e245
lib: initial implementation of an ECP5 EBR primitive
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Only the core unconditioned primitive right now, and still needs refining.
2024-08-17 15:43:36 -07:00
David Anderson
db30e4a23f
tasks.py: prettify output, support running partial synthesis
...
Partial synth is handy when writing gnarly Bluespec modules, because it
lets you inspect the Verilog output of the Bluespec compiler as well as
Yosys's compile output at various stages of synthesis, to see if things
are being produced the way you expect.
2024-08-17 15:41:21 -07:00
David Anderson
e6fa717507
Experiment comparing bsc-contrib's video timing generator with brute force
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Brute force is a naively written state machine that combines both horizontal
and vertical timings into one, in a way that unrolls comically badly. It's
obviously uncompetitive as-is, but I wanted to use that as a starting point
to see how much bsc and yosys would still be able to cope with it.
The result: the worse code takes much longer for bluespec to evaluate, and it
consumes ~4x the amount of logic elements after synthesis. Less terrible than
I expected, to be honest!
2024-08-15 00:22:51 -07:00
David Anderson
dad128b56b
Fix up some bugs in the Invoke script.
2024-08-15 00:22:30 -07:00
David Anderson
2efb40fa3d
Requirements.md: fix image insertion syntax
2024-08-14 09:44:14 -07:00
David Anderson
39e17f8e42
lib: add test helpers for timeouts and sequential test running
2024-08-14 09:39:42 -07:00
David Anderson
730d11ecea
Add tentative requirements document to capture requests.
2024-08-14 09:39:42 -07:00
David Anderson
e83f3a993c
add a simple build/test script
2024-08-14 09:39:42 -07:00
David Anderson
3111d069e6
Initial basic files
2024-08-13 22:24:20 -07:00
David Anderson
8f0e0dbbad
initial commit
2024-08-12 00:36:17 -07:00