gary/hardware/sentinel65x/PLL.bsv

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package PLL;
// Frequencies: FPGA 100MHz, CPU 8MHz, VGA 25MHz
//
// To regenerate, see 'inv genclk -h'
// Clocks are the various clocks used in GARY.
interface Clocks;
// main_clk is the internal clock that most of the design runs at.
interface Clock main_clk;
// cpu_clk is the clock generated and output for use by the 65X
// CPU. The system bus interface is clocked by cpu_clk.
interface Clock cpu_clk;
// vga_clk is the pixel clock for the video output.
interface Clock vga_clk;
// locked is whether the PLL has locked and is producing stable
// clocks.
//
// TODO: hook this into clock gating or global reset, to hold the
// FPGA in a safe state while the PLL starts up and locks.
(* always_ready *)
method Bool locked();
endinterface
// mkPLL takes in a reference clock signal and generates GARY's
// clocks. All the output clocks are in phase with main_clk,
// i.e. every posedge of cpu_clk and vga_clk is also a posedge of
// main_clk.
import "BVI" PLL =
module mkPLL(Clock clk, Clocks ifc);
default_clock no_clock;
default_reset no_reset;
input_clock ref_clk(CLK_REF, (* unused *)CLK_REF_GATE) = clk;
output_clock main_clk(CLK_MAIN);
output_clock cpu_clk(CLK_CPU);
output_clock vga_clk(CLK_VGA);
ancestor(cpu_clk, main_clk);
ancestor(vga_clk, main_clk);
method locked locked();
schedule locked CF locked;
endmodule
endpackage