50 lines
1.4 KiB
Plaintext
50 lines
1.4 KiB
Plaintext
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package PLL;
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// Frequencies: FPGA 100MHz, CPU 10MHz, VGA 25MHz
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//
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// To regenerate, see 'inv genclk -h'
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// Clocks are the various clocks used in GARY.
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interface Clocks;
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// main_clk is the internal clock that most of the design runs at.
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interface Clock main_clk;
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// cpu_clk is the clock generated and output for use by the 65X
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// CPU. The system bus interface is clocked by cpu_clk.
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interface Clock cpu_clk;
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// vga_clk is the pixel clock for the video output.
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interface Clock vga_clk;
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// locked is whether the PLL has locked and is producing stable
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// clocks.
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//
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// TODO: hook this into clock gating or global reset, to hold the
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// FPGA in a safe state while the PLL starts up and locks.
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(* always_ready *)
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method Bool locked();
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endinterface
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// mkPLL takes in a reference clock signal and generates GARY's
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// clocks. All the output clocks are in phase with main_clk,
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// i.e. every posedge of cpu_clk and vga_clk is also a posedge of
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// main_clk.
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import "BVI" PLL =
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module mkPLL(Clock clk, Clocks ifc);
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default_clock no_clock;
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default_reset no_reset;
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input_clock ref_clk(CLK_REF, (* unused *)CLK_REF_GATE) = clk;
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output_clock main_clk(CLK_MAIN);
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output_clock cpu_clk(CLK_CPU);
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output_clock vga_clk(CLK_VGA);
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ancestor(cpu_clk, main_clk);
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ancestor(vga_clk, main_clk);
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method locked locked();
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schedule locked CF locked;
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endmodule
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endpackage
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