gary/experiments/primitive_ram/Top.bsv

package Top;

import ECP5_RAM::*;

(* always_enabled *)
interface Top;
   (* prefix="" *)
   method Action putA((* port="adc_miso" *) Bool write, (* port="btn" *)Bit#(4) addr, (* port="sd_d" *) Bit#(4) data);
   (* prefix="" *)
   method Action putB((* port="flash_csn" *) Bool write, (* port="audio_l" *) Bit#(4) addr, (* port="audio_r" *) Bit#(4) data);
   (* result="led" *)
   method Bit#(8) read();
   //interface EBRPort#(Bit#(12), Bit#(4)) ram1;
   //interface EBRPort#(Bit#(12), Bit#(4)) ram2;
endinterface

(* synthesize,clock_prefix="clk_25mhz",reset_prefix="audio_v" *)
module mkTop(Top ifc);
   EBRPortConfig cfgA = defaultValue;
   cfgA.write_mode = Normal;
   cfgA.chip_select_addr = 5;
   EBRPortConfig cfgB = defaultValue;
   // cfgB.clk = tagged Valid clk2;
   // cfgB.rstN = tagged Valid rst2;
   cfgB.register_output = True;
   let r <- mkEBR(cfgA, cfgB);

   Wire#(Bit#(8)) out <- mkDWire(0);

   rule collect_output;
      out <= {r.portA.read, r.portB.read};
   endrule

   method Action putA(Bool write, Bit#(4) addr, Bit#(4) data);
      r.portA.put(0, write, addr, data);
   endmethod
   method Action putB(Bool write, Bit#(4) addr, Bit#(4) data);
      r.portB.put(0, write, addr, data);
   endmethod
   method Bit#(8) read();
      return out;
   endmethod
   //interface EBRPort ram1 = r.portA;
   //interface EBRPort ram2 = r.portB;
endmodule

endpackage