18 lines
397 B
Plaintext
18 lines
397 B
Plaintext
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package Top;
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import ECP5_RAM::*;
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(* synthesize *)
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module mkTop(ECP5_EBRCorePort#(Bit#(12), Bit#(8)));
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let clk <- exposeCurrentClock;
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let rstN <- exposeCurrentReset;
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ECP5_EBRPortConfig cfg = defaultValue;
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ECP5_EBRCore#(Bit#(12), Bit#(8), UInt#(12), UInt#(8)) ram <- mkECP5_EBRCoreByte(cfg, cfg);
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method put = ram.portA.put;
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method read = ram.portA.read;
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endmodule
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endpackage
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