2024-08-14 05:53:47 +02:00
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package Top;
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import ECP5_RAM::*;
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2024-08-14 05:53:47 +02:00
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(* always_enabled *)
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interface Top;
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method Action put(UInt#(3) select, Bool write, Bit#(12) address, Bit#(4) data);
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method Bit#(4) read();
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endinterface
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2024-08-14 05:53:47 +02:00
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2024-08-14 05:53:47 +02:00
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(* synthesize *)
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module mkTop(Clock extClk, Reset extRst, Top ifc);
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ECP5_EBRPortConfig cfgA = defaultValue;
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cfgA.clk = tagged Valid extClk;
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cfgA.rstN = tagged Valid extRst;
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ECP5_EBRPortConfig cfgB = defaultValue;
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ECP5_EBRCore#(Bit#(12), Bit#(4), UInt#(12), UInt#(4)) ram <- mkECP5_EBRCore(cfgA, cfgB);
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2024-08-14 05:53:47 +02:00
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method put = ram.portA.put;
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method read = ram.portA.read;
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endmodule
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endpackage
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