package Top;

import ECP5_RAM::*;

(* always_enabled *)
interface Top;
   method Action put(UInt#(3) select, Bool write, Bit#(12) address, Bit#(4) data);
   method Bit#(4) read();
endinterface

(* synthesize *)
module mkTop(Clock extClk, Reset extRst, Top ifc);
   ECP5_EBRPortConfig cfgA = defaultValue;
   cfgA.clk = tagged Valid extClk;
   cfgA.rstN = tagged Valid extRst;
   ECP5_EBRPortConfig cfgB = defaultValue;
   ECP5_EBRCore#(Bit#(12), Bit#(4), UInt#(12), UInt#(4)) ram <- mkECP5_EBRCore(cfgA, cfgB);

   method put = ram.portA.put;
   method read = ram.portA.read;
endmodule

endpackage