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Graphics Adapter for Retropixel Yeeting. An experiment for now, who knows what might happen.
92 Commits 1 Branch 0 Tags 604 KiB
Bluespec 67%
Verilog 19.9%
Go 6.7%
Python 4.3%
Perl 1.2%
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David Anderson 227526c2b1 lib/ECP5_RAM: invert reset signal going into the primitive 
Bluespec uses active-low reset signals, whereas the ECP5 primitives
use active-high. So this was holding the EBRs in reset after the rest
of the design was running. Oops.
 		2024-09-14 20:16:44 -07:00
experiments experiments/uart: wire up a top-level UART for ulx3s 2024-09-13 21:24:29 -07:00
hardware hardware/ulx3s: at last, a top-level design 2024-09-14 16:13:17 -07:00
images Add tentative requirements document to capture requests. 2024-08-14 09:39:42 -07:00
lib lib/ECP5_RAM: invert reset signal going into the primitive 2024-09-14 20:16:44 -07:00
scripts Grab the inout port fixer from bsc tree, wire it in 2024-09-06 21:26:39 -07:00
sim Add some early testing harness for the sim DP16KD 2024-08-30 22:14:10 -07:00
vram vram/VRAMCore: cycle using prime numbers in tests 2024-09-09 11:27:53 -07:00
.gitignore add a simple build/test script 2024-08-14 09:39:42 -07:00
.svlint.toml Add svlint config 2024-08-23 00:21:15 -07:00
LICENSE Initial basic files 2024-08-13 22:24:20 -07:00
Requirements.md Requirements.md: fix image insertion syntax 2024-08-14 09:44:14 -07:00
flake.lock flake.lock: update tools 2024-09-06 21:17:32 -07:00
flake.nix flake.nix: grab the GUI version of nextpnr 2024-09-13 21:25:01 -07:00
tasks.py tasks.py: support using nextpnr's "static" placer 2024-09-14 16:12:28 -07:00