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compare: dave:8d2261e245a96b1422c735f27860547e010620df
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3 changed files with 15 additions and 45 deletions
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18
experiments/primitive_ram/Top.bsv
View File

@ -2,19 +2,13 @@ package Top;
import ECP5_RAM::*;
(* always_enabled *)
interface Top;
method Action put(UInt#(3) select, Bool write, Bit#(12) address, Bit#(4) data);
method Bit#(4) read();
endinterface
(* synthesize *)
module mkTop(Clock extClk, Reset extRst, Top ifc);
ECP5_EBRPortConfig cfgA = defaultValue;
cfgA.clk = tagged Valid extClk;
cfgA.rstN = tagged Valid extRst;
ECP5_EBRPortConfig cfgB = defaultValue;
ECP5_EBRCore#(Bit#(12), Bit#(4), UInt#(12), UInt#(4)) ram <- mkECP5_EBRCore(cfgA, cfgB);
module mkTop(ECP5_EBRCorePort#(Bit#(12), Bit#(8)));
let clk <- exposeCurrentClock;
let rstN <- exposeCurrentReset;
ECP5_EBRPortConfig cfg = defaultValue;
ECP5_EBRCore#(Bit#(12), Bit#(8), UInt#(12), UInt#(8)) ram <- mkECP5_EBRCoreByte(cfg, cfg);
method put = ram.portA.put;
method read = ram.portA.read;

40
lib/ECP5_RAM.bsv
View File

@ -17,12 +17,8 @@ typedef enum {
// ECP5_EBRPortConfig is the static configuration of an EBR port.
typedef struct {
// clk, if specified, is the Clock to use for the port. If
// unspecified, uses the module default clock.
Maybe#(Clock) clk;
// rstN, if specified, is the Reset to use for the port. If
// unspecified, uses the module default reset.
Maybe#(Reset) rstN;
Clock clk;
Reset rstN;
// By default, ECP5 EBRs only register the input address and write
// data, giving a 1-cycle latency for operations. If
// registered_output is true, the output value is also registered,
@ -38,8 +34,8 @@ typedef struct {
instance DefaultValue#(ECP5_EBRPortConfig);
defaultValue = ECP5_EBRPortConfig{
clk: defaultValue,
rstN: defaultValue,
clk: noClock,
rstN: noReset,
registered_output: False,
chip_select_addr: 0,
write_mode: Normal
@ -72,34 +68,14 @@ import "BVI" ECP5_RAM =
Integer portB_width)
(ECP5_EBRCoreInner);
let defClk <- exposeCurrentClock;
let defRstN <- exposeCurrentReset;
let portA_bsv_clock = case (port_a.clk) matches
tagged Invalid: defClk;
tagged Valid .clk: clk;
endcase;
let portA_bsv_rstN = case (port_a.rstN) matches
tagged Invalid: defRstN;
tagged Valid .rstN: rstN;
endcase;
let portB_bsv_clock = case (port_b.clk) matches
tagged Invalid: defClk;
tagged Valid .clk: clk;
endcase;
let portB_bsv_rstN = case (port_b.rstN) matches
tagged Invalid: defRstN;
tagged Valid .rstN: rstN;
endcase;
default_clock no_clock;
default_reset no_reset;
input_clock portA_clk(CLKA, (* unused *)CLKA_GATE) = portA_bsv_clock;
input_reset portA_rstN(RSTA) clocked_by(portA_clk) = portA_bsv_rstN;
input_clock portA_clk(CLKA, (* unused *)CLKA_GATE) = port_a.clk;
input_reset portA_rstN(RSTA) clocked_by(portA_clk) = port_a.rstN;
input_clock portB_clk(CLKB, (* unused *)CLKB_GATE) = portB_bsv_clock;
input_reset portB_rstN(RSTB) clocked_by(portB_clk) = portB_bsv_rstN;
input_clock portB_clk(CLKB, (* unused *)CLKB_GATE) = port_b.clk;
input_reset portB_rstN(RSTB) clocked_by(portB_clk) = port_b.rstN;
parameter DATA_WIDTH_A = portA_width;
parameter REGMODE_A = port_a.registered_output ? "OUTREG" : "NOREG";

2
lib/ECP5_RAM.v
View File

@ -160,7 +160,7 @@ module ECP5_RAM(CLKA,
.CSA2(CSA[2]),
.CSA1(CSA[1]),
.CSA0(CSA[0]),
.RSTB(RSTB),
.RSTB(RSTA),
.DOB17(DOB[17]),
.DOB16(DOB[16]),
.DOB15(DOB[15]),