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a69cc878ce
Author | SHA1 | Date |
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David Anderson | a69cc878ce | |
David Anderson | a23661a449 | |
David Anderson | e64b990f80 |
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@ -2,13 +2,19 @@ package Top;
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import ECP5_RAM::*;
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(* synthesize *)
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module mkTop(ECP5_EBRCorePort#(Bit#(12), Bit#(8)));
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let clk <- exposeCurrentClock;
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let rstN <- exposeCurrentReset;
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(* always_enabled *)
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interface Top;
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method Action put(UInt#(3) select, Bool write, Bit#(12) address, Bit#(4) data);
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method Bit#(4) read();
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endinterface
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ECP5_EBRPortConfig cfg = defaultValue;
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ECP5_EBRCore#(Bit#(12), Bit#(8), UInt#(12), UInt#(8)) ram <- mkECP5_EBRCoreByte(cfg, cfg);
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(* synthesize *)
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module mkTop(Clock extClk, Reset extRst, Top ifc);
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ECP5_EBRPortConfig cfgA = defaultValue;
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cfgA.clk = tagged Valid extClk;
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cfgA.rstN = tagged Valid extRst;
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ECP5_EBRPortConfig cfgB = defaultValue;
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ECP5_EBRCore#(Bit#(12), Bit#(4), UInt#(12), UInt#(4)) ram <- mkECP5_EBRCore(cfgA, cfgB);
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method put = ram.portA.put;
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method read = ram.portA.read;
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@ -17,8 +17,12 @@ typedef enum {
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// ECP5_EBRPortConfig is the static configuration of an EBR port.
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typedef struct {
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Clock clk;
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Reset rstN;
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// clk, if specified, is the Clock to use for the port. If
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// unspecified, uses the module default clock.
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Maybe#(Clock) clk;
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// rstN, if specified, is the Reset to use for the port. If
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// unspecified, uses the module default reset.
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Maybe#(Reset) rstN;
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// By default, ECP5 EBRs only register the input address and write
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// data, giving a 1-cycle latency for operations. If
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// registered_output is true, the output value is also registered,
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@ -34,8 +38,8 @@ typedef struct {
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instance DefaultValue#(ECP5_EBRPortConfig);
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defaultValue = ECP5_EBRPortConfig{
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clk: noClock,
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rstN: noReset,
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clk: defaultValue,
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rstN: defaultValue,
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registered_output: False,
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chip_select_addr: 0,
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write_mode: Normal
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@ -68,14 +72,34 @@ import "BVI" ECP5_RAM =
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Integer portB_width)
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(ECP5_EBRCoreInner);
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let defClk <- exposeCurrentClock;
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let defRstN <- exposeCurrentReset;
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let portA_bsv_clock = case (port_a.clk) matches
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tagged Invalid: defClk;
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tagged Valid .clk: clk;
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endcase;
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let portA_bsv_rstN = case (port_a.rstN) matches
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tagged Invalid: defRstN;
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tagged Valid .rstN: rstN;
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endcase;
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let portB_bsv_clock = case (port_b.clk) matches
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tagged Invalid: defClk;
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tagged Valid .clk: clk;
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endcase;
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let portB_bsv_rstN = case (port_b.rstN) matches
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tagged Invalid: defRstN;
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tagged Valid .rstN: rstN;
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endcase;
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default_clock no_clock;
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default_reset no_reset;
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input_clock portA_clk(CLKA, (* unused *)CLKA_GATE) = port_a.clk;
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input_reset portA_rstN(RSTA) clocked_by(portA_clk) = port_a.rstN;
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input_clock portA_clk(CLKA, (* unused *)CLKA_GATE) = portA_bsv_clock;
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input_reset portA_rstN(RSTA) clocked_by(portA_clk) = portA_bsv_rstN;
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input_clock portB_clk(CLKB, (* unused *)CLKB_GATE) = port_b.clk;
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input_reset portB_rstN(RSTB) clocked_by(portB_clk) = port_b.rstN;
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input_clock portB_clk(CLKB, (* unused *)CLKB_GATE) = portB_bsv_clock;
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input_reset portB_rstN(RSTB) clocked_by(portB_clk) = portB_bsv_rstN;
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parameter DATA_WIDTH_A = portA_width;
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parameter REGMODE_A = port_a.registered_output ? "OUTREG" : "NOREG";
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@ -160,7 +160,7 @@ module ECP5_RAM(CLKA,
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.CSA2(CSA[2]),
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.CSA1(CSA[1]),
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.CSA0(CSA[0]),
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.RSTB(RSTA),
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.RSTB(RSTB),
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.DOB17(DOB[17]),
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.DOB16(DOB[16]),
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.DOB15(DOB[15]),
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