183 lines
7.8 KiB
Verilog
183 lines
7.8 KiB
Verilog
module ECP5_RAM(CLKA,
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CEA,
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OCEA,
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WEA,
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DIA,
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ADA,
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CSA,
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RSTA,
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DOA,
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CLKB,
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CEB,
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OCEB,
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WEB,
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DIB,
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ADB,
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CSB,
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RSTB,
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DOB);
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parameter GSR = "AUTO";
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parameter RESETMODE = "SYNC";
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parameter ASYNC_RESET_RELEASE = "SYNC";
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parameter DATA_WIDTH_A = 18;
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parameter REGMODE_A = "NOREG";
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parameter WRITEMODE_A = "NORMAL";
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parameter CSDECODE_A = "0b000";
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parameter DATA_WIDTH_B = 18;
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parameter REGMODE_B = "NOREG";
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parameter WRITEMODE_B = "NORMAL";
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parameter CSDECODE_B = "0b000";
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input CLKA;
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input CEA;
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input OCEA;
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input WEA;
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input [17:0] DIA;
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input [13:0] ADA;
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input [2:0] CSA;
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input RSTA;
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output [17:0] DOA;
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input CLKB;
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input CEB;
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input OCEB;
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input WEB;
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input [17:0] DIB;
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input [13:0] ADB;
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input [2:0] CSB;
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input RSTB;
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output [17:0] DOB;
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DP16KD#(.GSR(GSR),
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.RESETMODE(RESETMODE),
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.ASYNC_RESET_RELEASE(ASYNC_RESET_RELEASE),
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.DATA_WIDTH_A(DATA_WIDTH_A),
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.REGMODE_A(REGMODE_A),
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.WRITEMODE_A(WRITEMODE_A),
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.CSDECODE_A(CSDECODE_A),
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.DATA_WIDTH_B(DATA_WIDTH_B),
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.REGMODE_B(REGMODE_B),
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.WRITEMODE_B(WRITEMODE_B),
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.CSDECODE_B(CSDECODE_B)) ram(.CLKA(CLKA),
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.CEA(CEA),
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.OCEA(OCEA),
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.WEA(WEA),
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.DIA17(DIA[17]),
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.DIA16(DIA[16]),
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.DIA15(DIA[15]),
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.DIA14(DIA[14]),
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.DIA13(DIA[13]),
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.DIA12(DIA[12]),
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.DIA11(DIA[11]),
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.DIA10(DIA[10]),
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.DIA9(DIA[9]),
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.DIA8(DIA[8]),
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.DIA7(DIA[7]),
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.DIA6(DIA[6]),
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.DIA5(DIA[5]),
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.DIA4(DIA[4]),
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.DIA3(DIA[3]),
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.DIA2(DIA[2]),
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.DIA1(DIA[1]),
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.DIA0(DIA[0]),
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.ADA13(ADA[13]),
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.ADA12(ADA[12]),
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.ADA11(ADA[11]),
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.ADA10(ADA[10]),
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.ADA9(ADA[9]),
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.ADA8(ADA[8]),
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.ADA7(ADA[7]),
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.ADA6(ADA[6]),
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.ADA5(ADA[5]),
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.ADA4(ADA[4]),
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.ADA3(ADA[3]),
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.ADA2(ADA[2]),
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.ADA1(ADA[1]),
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.ADA0(ADA[0]),
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.CSA2(CSA[2]),
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.CSA1(CSA[1]),
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.CSA0(CSA[0]),
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.RSTA(RSTA),
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.DOA17(DOA[17]),
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.DOA16(DOA[16]),
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.DOA15(DOA[15]),
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.DOA14(DOA[14]),
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.DOA13(DOA[13]),
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.DOA12(DOA[12]),
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.DOA11(DOA[11]),
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.DOA10(DOA[10]),
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.DOA9(DOA[9]),
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.DOA8(DOA[8]),
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.DOA7(DOA[7]),
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.DOA6(DOA[6]),
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.DOA5(DOA[5]),
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.DOA4(DOA[4]),
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.DOA3(DOA[3]),
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.DOA2(DOA[2]),
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.DOA1(DOA[1]),
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.DOA0(DOA[0]),
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.CLKB(CLKB),
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.CEB(CEB),
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.OCEB(OCEB),
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.WEB(WEB),
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.DIB17(DIB[17]),
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.DIB16(DIB[16]),
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.DIB15(DIB[15]),
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.DIB14(DIB[14]),
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.DIB13(DIB[13]),
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.DIB12(DIB[12]),
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.DIB11(DIB[11]),
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.DIB10(DIB[10]),
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.DIB9(DIB[9]),
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.DIB8(DIB[8]),
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.DIB7(DIB[7]),
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.DIB6(DIB[6]),
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.DIB5(DIB[5]),
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.DIB4(DIB[4]),
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.DIB3(DIB[3]),
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.DIB2(DIB[2]),
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.DIB1(DIB[1]),
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.DIB0(DIB[0]),
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.ADB13(ADB[13]),
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.ADB12(ADB[12]),
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.ADB11(ADB[11]),
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.ADB10(ADB[10]),
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.ADB9(ADB[9]),
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.ADB8(ADB[8]),
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.ADB7(ADB[7]),
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.ADB6(ADB[6]),
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.ADB5(ADB[5]),
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.ADB4(ADB[4]),
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.ADB3(ADB[3]),
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.ADB2(ADB[2]),
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.ADB1(ADB[1]),
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.ADB0(ADB[0]),
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.CSA2(CSA[2]),
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.CSA1(CSA[1]),
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.CSA0(CSA[0]),
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.RSTB(RSTA),
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.DOB17(DOB[17]),
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.DOB16(DOB[16]),
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.DOB15(DOB[15]),
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.DOB14(DOB[14]),
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.DOB13(DOB[13]),
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.DOB12(DOB[12]),
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.DOB11(DOB[11]),
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.DOB10(DOB[10]),
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.DOB9(DOB[9]),
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.DOB8(DOB[8]),
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.DOB7(DOB[7]),
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.DOB6(DOB[6]),
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.DOB5(DOB[5]),
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.DOB4(DOB[4]),
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.DOB3(DOB[3]),
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.DOB2(DOB[2]),
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.DOB1(DOB[1]),
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.DOB0(DOB[0]));
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endmodule
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