Commit Graph

21 Commits

Author SHA1 Message Date
David Anderson b73a211ec4 lib/ECP5_RAM: clean up old core, fix error in module docstring 2024-08-20 19:25:04 -07:00
David Anderson 1ccd1b0072 lib/DelayLine: add a bit more documentation 2024-08-20 09:15:52 -07:00
David Anderson 2a8689564c tasks.py: remove debug message 2024-08-20 09:13:36 -07:00
David Anderson 5df41d4b94 lib: use DelayLine in ECP5_RAM
Cleans up the code nicely, and still produces the correct logic.
2024-08-20 00:54:50 -07:00
David Anderson f1e705fd31 lib: add more documentation 2024-08-20 00:29:32 -07:00
David Anderson 85e27554ec lib: add a DelayLine module
A delay line takes a write and echoes it back N cycles later,
with N fixed at compile time. It's a handy primitive to have
when wrapping Verilog blackbox modules because the blackbox
often specifies something like having 2 cycles of latency,
and so you need to bubble the fact that a write occurred 2
cycles ago through to the output so that you can wire up the
right implicit conditions.
2024-08-19 23:00:15 -07:00
David Anderson 27da4958d2 experiments/rmw_ram: document failed/paused memory trickery experiments 2024-08-19 15:39:43 -07:00
David Anderson da6ea4cf42 lib: flesh out the ECP5 EBR modules, write copious documentation 2024-08-18 16:12:57 -07:00
David Anderson a69cc878ce experiments/primitive_ram: customize the clock/reset of one of the RAM ports 2024-08-17 16:41:24 -07:00
David Anderson a23661a449 lib: default clocks and resets to the ambient ones from context
Callers can still specify whacky cross-domain RAMs in the cfg, but the
default is what you usually want: a dual-port RAM with both ports in the
caller's clock/reset domain.
2024-08-17 16:39:45 -07:00
David Anderson e64b990f80 lib: fix port B reset wiring for ECP5_RAM 2024-08-17 16:38:52 -07:00
David Anderson 8d2261e245 lib: initial implementation of an ECP5 EBR primitive
Only the core unconditioned primitive right now, and still needs refining.
2024-08-17 15:43:36 -07:00
David Anderson db30e4a23f tasks.py: prettify output, support running partial synthesis
Partial synth is handy when writing gnarly Bluespec modules, because it
lets you inspect the Verilog output of the Bluespec compiler as well as
Yosys's compile output at various stages of synthesis, to see if things
are being produced the way you expect.
2024-08-17 15:41:21 -07:00
David Anderson e6fa717507 Experiment comparing bsc-contrib's video timing generator with brute force
Brute force is a naively written state machine that combines both horizontal
and vertical timings into one, in a way that unrolls comically badly. It's
obviously uncompetitive as-is, but I wanted to use that as a starting point
to see how much bsc and yosys would still be able to cope with it.

The result: the worse code takes much longer for bluespec to evaluate, and it
consumes ~4x the amount of logic elements after synthesis. Less terrible than
I expected, to be honest!
2024-08-15 00:22:51 -07:00
David Anderson dad128b56b Fix up some bugs in the Invoke script. 2024-08-15 00:22:30 -07:00
David Anderson 2efb40fa3d Requirements.md: fix image insertion syntax 2024-08-14 09:44:14 -07:00
David Anderson 39e17f8e42 lib: add test helpers for timeouts and sequential test running 2024-08-14 09:39:42 -07:00
David Anderson 730d11ecea Add tentative requirements document to capture requests. 2024-08-14 09:39:42 -07:00
David Anderson e83f3a993c add a simple build/test script 2024-08-14 09:39:42 -07:00
David Anderson 3111d069e6 Initial basic files 2024-08-13 22:24:20 -07:00
David Anderson 8f0e0dbbad initial commit 2024-08-12 00:36:17 -07:00