Commit Graph

15 Commits

Author SHA1 Message Date
David Anderson 77b772c7ee tasks.py: improve handling of Bluespec libdirs
To help divvy up the sources better, the build now makes a libpath
consisting of all directories that have bsv files in them, with a few
exceptions: hardware subdirs are target-specific so only get used if
they're the current build target. Experiments are random crap so get
the same treatment. And the 'sim' dir is only test helpers, so they
only get pulled in by tests.
2024-09-07 10:31:32 -07:00
David Anderson 6fd040565c Grab the inout port fixer from bsc tree, wire it in
Yosys doesn't understand Verilog-2001 port aliases. Unfortunately
bsc uses those to represent inout ports because it's the only way
to represent a particular kind of shared bus in Verilog source code.

Thankfully, a kind soul at Bluespec Inc made a perl script that
transforms the port alias construct into regular verilog-1995, which
works fine in cases like mine where the only user of the inout port
is a TriState module which tears it apart into separate
input/output/enable signals for the rest of bsc to work with.
2024-09-06 21:26:39 -07:00
David Anderson 0005ad6fe5 sentinel65x/PLL: update PLL settings, fix generator 2024-09-06 21:18:00 -07:00
David Anderson 930f9f7078 sentinel65x: start of Sentinel 65X top-level glue, with a PLL module
The PLL generates a 100MHz clock for GARY, 10MHz for the CPU and
system bus, and 25MHz for VGA out.
2024-09-06 16:21:25 -07:00
David Anderson 7560199251 tasks: support running nextpnr with a generic ulx3s pin map
This is handy for quick experiments, rather than having to define a
bespoke pin map for each experiment.
2024-09-06 16:11:03 -07:00
David Anderson 5e22d03e15 vram: implement a MemoryArbiter for VRAM 2024-09-05 23:39:21 -07:00
David Anderson 2cd172cc73 tasks.py: add sim directory when running tests
So that bluesim can find the DP16KD simulation model.
2024-08-31 00:00:59 -07:00
David Anderson a4a10becbf tasks.py: print one more intermediate output path 2024-08-30 20:06:36 -07:00
David Anderson 5d16ce23aa tasks.py: adjust yosys script 2024-08-23 00:20:31 -07:00
David Anderson 2a8689564c tasks.py: remove debug message 2024-08-20 09:13:36 -07:00
David Anderson 5df41d4b94 lib: use DelayLine in ECP5_RAM
Cleans up the code nicely, and still produces the correct logic.
2024-08-20 00:54:50 -07:00
David Anderson 85e27554ec lib: add a DelayLine module
A delay line takes a write and echoes it back N cycles later,
with N fixed at compile time. It's a handy primitive to have
when wrapping Verilog blackbox modules because the blackbox
often specifies something like having 2 cycles of latency,
and so you need to bubble the fact that a write occurred 2
cycles ago through to the output so that you can wire up the
right implicit conditions.
2024-08-19 23:00:15 -07:00
David Anderson db30e4a23f tasks.py: prettify output, support running partial synthesis
Partial synth is handy when writing gnarly Bluespec modules, because it
lets you inspect the Verilog output of the Bluespec compiler as well as
Yosys's compile output at various stages of synthesis, to see if things
are being produced the way you expect.
2024-08-17 15:41:21 -07:00
David Anderson dad128b56b Fix up some bugs in the Invoke script. 2024-08-15 00:22:30 -07:00
David Anderson e83f3a993c add a simple build/test script 2024-08-14 09:39:42 -07:00