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experiments/primitive_ram: clean up old testing code

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David Anderson 2024-09-06 16:23:47 -07:00
parent 930f9f7078
commit f61328dac4
1 changed files with 0 additions and 6 deletions
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6
experiments/primitive_ram/Top.bsv
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@ -10,8 +10,6 @@ interface Top;
method Action putB((* port="flash_csn" *) Bool write, (* port="audio_l" *) Bit#(4) addr, (* port="audio_r" *) Bit#(4) data); method Action putB((* port="flash_csn" *) Bool write, (* port="audio_l" *) Bit#(4) addr, (* port="audio_r" *) Bit#(4) data);
(* result="led" *) (* result="led" *)
method Bit#(8) read(); method Bit#(8) read();
//interface EBRPort#(Bit#(12), Bit#(4)) ram1;
//interface EBRPort#(Bit#(12), Bit#(4)) ram2;
endinterface endinterface
(* synthesize,clock_prefix="clk_25mhz",reset_prefix="audio_v" *) (* synthesize,clock_prefix="clk_25mhz",reset_prefix="audio_v" *)
@ -20,8 +18,6 @@ module mkTop(Top ifc);
cfgA.write_mode = Normal; cfgA.write_mode = Normal;
cfgA.chip_select_addr = 5; cfgA.chip_select_addr = 5;
EBRPortConfig cfgB = defaultValue; EBRPortConfig cfgB = defaultValue;
// cfgB.clk = tagged Valid clk2;
// cfgB.rstN = tagged Valid rst2;
cfgB.register_output = True; cfgB.register_output = True;
let r <- mkEBR(cfgA, cfgB); let r <- mkEBR(cfgA, cfgB);
@ -40,8 +36,6 @@ module mkTop(Top ifc);
method Bit#(8) read(); method Bit#(8) read();
return out; return out;
endmethod endmethod
//interface EBRPort ram1 = r.portA;
//interface EBRPort ram2 = r.portB;
endmodule endmodule
endpackage endpackage