tasks.py: improve handling of Bluespec libdirs
To help divvy up the sources better, the build now makes a libpath consisting of all directories that have bsv files in them, with a few exceptions: hardware subdirs are target-specific so only get used if they're the current build target. Experiments are random crap so get the same treatment. And the 'sim' dir is only test helpers, so they only get pulled in by tests.
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25d1806590
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77b772c7ee
45
tasks.py
45
tasks.py
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@ -24,18 +24,45 @@ def bsc_root(c):
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return Path(l[len(dir_prefix):])
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return Path(l[len(dir_prefix):])
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raise RuntimeError("Couldn't locate Bluespec root dir")
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raise RuntimeError("Couldn't locate Bluespec root dir")
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def find_verilog_modules(c, modules):
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def bluespec_libdirs(*extras):
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libpaths = [Path("lib"), bsc_root(c) / "Verilog"]
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ret = []
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for x in extras:
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x = Path(x)
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if not x.is_dir():
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x = x.parent
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if not x.is_dir():
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raise ValueError(f"unknown libdir thing {x}")
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ret.append(x)
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bsv_dirs = list(sorted(set(p.parent for p in Path("").glob("**/*.bsv"))))
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exclude_trees = [Path("hardware"), Path("experiments"), Path("sim")] + ret
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for d in bsv_dirs:
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if any(d.is_relative_to(x) for x in exclude_trees):
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continue
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ret.append(d)
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ret.append("%/Libraries")
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return ":".join(str(s) for s in ret)
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def find_verilog_modules(c, target_dir, modules):
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preferred_libpaths = [target_dir, Path("lib"), bsc_root(c) / "Verilog"]
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ret = []
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ret = []
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for module in modules:
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for module in modules:
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module_path = None
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module_path = None
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verilog_path = Path(module).with_suffix(".v")
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# Try preferred libpaths first.
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for p in libpaths:
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for p in libpaths:
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f = p / Path(module).with_suffix(".v")
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f = p / verilog_path
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if f.is_file():
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if f.is_file():
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module_path = f
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module_path = f
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break
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break
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if module_path is None:
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if module_path is None:
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# Not in preferred paths, accept anywhere now.
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matches = Path("").glob(f"**/{module}.v")
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if len(matches) > 1:
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raise RuntimeError(f"Multiple candidates for verilog module {module}: {matches}")
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elif len(matches) == 0:
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raise RuntimeError(f"Cannot find verilog module {module} in {libpaths}")
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raise RuntimeError(f"Cannot find verilog module {module} in {libpaths}")
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module_path = matches[0]
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ret.append(module_path)
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ret.append(module_path)
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return ret
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return ret
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@ -82,14 +109,16 @@ def phase(name):
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print("")
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print("")
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@task
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@task
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def build(c, target="."):
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def build(c, target):
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phase("Compile Bluespec")
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phase("Compile Bluespec")
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verilog_files = []
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verilog_files = []
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for target in expand_build_target(target):
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for target in expand_build_target(target):
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out_info, out_verilog, out_bsc = ensure_build_dirs(target, "info", "verilog", "bsc")
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out_info, out_verilog, out_bsc = ensure_build_dirs(target, "info", "verilog", "bsc")
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libdirs = bluespec_libdirs(target)
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print(f"Building {target}")
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print(f"Building {target}")
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c.run(f"bsc -aggressive-conditions -check-assert -remove-dollar -remove-empty-rules -remove-false-rules -remove-starved-rules -verilog-filter scripts/basicinout.pl -show-method-conf -show-method-bvi -u -verilog -info-dir {out_info} -vdir {out_verilog} -bdir {out_bsc} -p {target.parent}:vram:lib:%/Libraries -show-module-use -show-compiles {target}")
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print(f"Libdirs: {libdirs.replace(':', ', ')}")
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c.run(f"bsc -aggressive-conditions -check-assert -remove-dollar -remove-empty-rules -remove-false-rules -remove-starved-rules -verilog-filter scripts/basicinout.pl -show-method-conf -show-method-bvi -u -verilog -info-dir {out_info} -vdir {out_verilog} -bdir {out_bsc} -p {libdirs} -show-module-use -show-compiles {target}")
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module_name = Path(f"mk{target.stem}")
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module_name = Path(f"mk{target.stem}")
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verilog_main_file = out_verilog / module_name.with_suffix(".v")
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verilog_main_file = out_verilog / module_name.with_suffix(".v")
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@ -98,7 +127,7 @@ def build(c, target="."):
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use_file = out_verilog / module_name.with_suffix(".use")
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use_file = out_verilog / module_name.with_suffix(".use")
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if use_file.is_file():
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if use_file.is_file():
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with open(out_verilog / module_name.with_suffix(".use")) as f:
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with open(out_verilog / module_name.with_suffix(".use")) as f:
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verilog_files.extend(find_verilog_modules(c, f.read().splitlines()))
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verilog_files.extend(find_verilog_modules(c, target.parent, f.read().splitlines()))
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if verilog_files:
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if verilog_files:
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print("\nVerilog files for synthesis:")
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print("\nVerilog files for synthesis:")
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@ -187,7 +216,9 @@ def synth(c, target):
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def test(c, target):
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def test(c, target):
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for target in expand_test_target(target):
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for target in expand_test_target(target):
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out_info, out_sim, out_bsc = ensure_build_dirs(target, "info", "sim", "bsc")
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out_info, out_sim, out_bsc = ensure_build_dirs(target, "info", "sim", "bsc")
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c.run(f"bsc -show-schedule -aggressive-conditions -check-assert -u -sim -info-dir {out_info} -simdir {out_sim} -bdir {out_bsc} -g mkTB -p {target.parent}:lib:sim:%/Libraries {target}")
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libdirs = bluespec_libdirs(target, "sim")
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print(f"Libdirs: {libdirs.replace(':', ', ')}")
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c.run(f"bsc -show-schedule -aggressive-conditions -check-assert -u -sim -info-dir {out_info} -simdir {out_sim} -bdir {out_bsc} -g mkTB -p {libdirs} {target}")
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exec = out_sim / "TB"
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exec = out_sim / "TB"
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c.run(f"bsc -p {out_bsc} -sim -simdir {out_sim} -e mkTB -o {exec}")
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c.run(f"bsc -p {out_bsc} -sim -simdir {out_sim} -e mkTB -o {exec}")
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testdata = out_sim / "testdata"
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testdata = out_sim / "testdata"
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