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lib/ECP5_RAM: invert reset signal going into the primitive 

Bluespec uses active-low reset signals, whereas the ECP5 primitives
use active-high. So this was holding the EBRs in reset after the rest
of the design was running. Oops.
This commit is contained in:
David Anderson 2024-09-14 16:40:14 -07:00
parent 8937e27d18
commit 227526c2b1
1 changed files with 2 additions and 2 deletions
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4
lib/ECP5_RAM.v
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@ -42,7 +42,7 @@ module ECP5_RAM#(
.REGMODE_B(REGMODE_B),
.WRITEMODE_B(WRITEMODE_B),
.CSDECODE_B(CSDECODE_B)
) ram(.CLKA(CLKA), .RSTA(RSTA), .CEA(CEA), .OCEA(OCEA), .WEA(WEA),
) ram(.CLKA(CLKA), .RSTA(!RSTA), .CEA(CEA), .OCEA(OCEA), .WEA(WEA),
.CSA2(CSA[2]), .CSA1(CSA[1]), .CSA0(CSA[0]),
.ADA13(ADA[13]), .ADA12(ADA[12]), .ADA11(ADA[11]), .ADA10(ADA[10]), .ADA9(ADA[9]),
.ADA8(ADA[8]), .ADA7(ADA[7]), .ADA6(ADA[6]), .ADA5(ADA[5]), .ADA4(ADA[4]),
@ -56,7 +56,7 @@ module ECP5_RAM#(
.DOA7(DOA[7]), .DOA6(DOA[6]), .DOA5(DOA[5]), .DOA4(DOA[4]), .DOA3(DOA[3]),
.DOA2(DOA[2]), .DOA1(DOA[1]), .DOA0(DOA[0]),
.CLKB(CLKB), .RSTB(RSTB), .CEB(CEB), .OCEB(OCEB), .WEB(WEB),
.CLKB(CLKB), .RSTB(!RSTB), .CEB(CEB), .OCEB(OCEB), .WEB(WEB),
.CSA2(CSA[2]), .CSA1(CSA[1]), .CSA0(CSA[0]),
.ADB13(ADB[13]), .ADB12(ADB[12]), .ADB11(ADB[11]), .ADB10(ADB[10]), .ADB9(ADB[9]),
.ADB8(ADB[8]), .ADB7(ADB[7]), .ADB6(ADB[6]), .ADB5(ADB[5]), .ADB4(ADB[4]),