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gary/lib/Testing.bsv

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lib: add test helpers for timeouts and sequential test running
2024-08-14 05:53:47 +02:00
package Testing;
import Assert::*;
import StmtFSM::*;
lib: add a DelayLine module A delay line takes a write and echoes it back N cycles later, with N fixed at compile time. It's a handy primitive to have when wrapping Verilog blackbox modules because the blackbox often specifies something like having 2 cycles of latency, and so you need to bubble the fact that a write occurred 2 cycles ago through to the output so that you can wire up the right implicit conditions.
2024-08-14 05:53:47 +02:00
interface TestCycleLimiter;
method Bit#(32) cycles();
lib: add test helpers for timeouts and sequential test running
2024-08-14 05:53:47 +02:00
lib: add a DelayLine module A delay line takes a write and echoes it back N cycles later, with N fixed at compile time. It's a handy primitive to have when wrapping Verilog blackbox modules because the blackbox often specifies something like having 2 cycles of latency, and so you need to bubble the fact that a write occurred 2 cycles ago through to the output so that you can wire up the right implicit conditions.
2024-08-14 05:53:47 +02:00
method Bit#(32) count();
method Action reset_count();
endinterface
module mkTestCycleLimiter#(Integer max_cycles)(TestCycleLimiter);
Bit#(32) max = fromInteger(max_cycles);
Reg#(Bit#(32)) cnt <- mkReg(0);
Reg#(Bit#(32)) lastReset <- mkReg(0);
(* no_implicit_conditions, fire_when_enabled *)
rule count_up;
dynamicAssert(cnt < max, "FAIL: test timed out");
cnt <= cnt+1;
lib: add test helpers for timeouts and sequential test running
2024-08-14 05:53:47 +02:00
endrule
lib: add a DelayLine module A delay line takes a write and echoes it back N cycles later, with N fixed at compile time. It's a handy primitive to have when wrapping Verilog blackbox modules because the blackbox often specifies something like having 2 cycles of latency, and so you need to bubble the fact that a write occurred 2 cycles ago through to the output so that you can wire up the right implicit conditions.
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method cycles = cnt._read;
method Bit#(32) count();
return cnt - lastReset;
endmethod
method Action reset_count();
lastReset <= cnt;
endmethod
lib: add test helpers for timeouts and sequential test running
2024-08-14 05:53:47 +02:00
endmodule
module mkTest#(String name, RStmt#(Bit#(0)) test)();
mkAutoFSM(seq
$display("RUN ", name);
test;
$display("OK ", name);
endseq);
endmodule
endpackage