forked from Sentinel65X/Sentinel65X-Handbook
1.2 KiB
Executable File
1.2 KiB
Executable File
Table of Contents
Clock Port
The Sentinel 65X clock port is a small, 28-pin female pin header on the mainboard, which exposes the system's debug serial line, I2C bus, reset and main interrupt lines, PHI2
clock signal, and a 64-address memory-mapped I/O region, mapped to memory beginning at 0x00DFC0
. This region of uncommitted expansion is reserved for the use of user-installed clock port accessories.
The clock port's pin header has two rows, and a pin and row pitch of 2.54mm.
Pinout
The clock port's pinout, as seen from above, is shown in the following table:
Pin | Label | Label | Pin | |
---|---|---|---|---|
1 | GND | +3.3V | 2 | |
3 | TXD | SCL | 4 | |
5 | RXD | SDA | 6 | |
7 | /CTS | /RES | 8 | |
9 | /RTS | /IRQ | 10 | |
11 | PHI2 | /CS1 | 12 | |
13 | /RD | /WR | 14 | |
15 | A5 | A4 | 16 | |
17 | A3 | A2 | 18 | |
19 | A1 | A0 | 20 | |
21 | D7 | D6 | 22 | |
23 | D5 | D4 | 24 | |
25 | D3 | D2 | 26 | |
27 | D1 | D0 | 28 |